Low-Voltage Embedded RAMs in Nanometer Era
Summary :
Low-voltage nanometer-scale embedded RAM cells are described. First, low-voltage RAM cells are compared in terms of cell size, threshold voltage for MOS transistor, and signal charge. Second, the solution for 6T and 4T SRAM cells to widen the voltage margin are investigated, especially the advantages with a back-gate controlled thin buried-oxide fully-depleted (FD) SOI are presented. Then, DRAM approach with a novel twin-cell is discussed in terms of improving the retention time and low-voltage operation. These low-voltage cell technologies are the promising candidates for future embedded RAMs.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E90-C No.4 pp.735-742
- Publication Date
- 2007/04/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1093/ietele/e90-c.4.735
- Type of Manuscript
- Special Section INVITED PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies)
- Category
Authors
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Takayuki KAWAHARA, "Low-Voltage Embedded RAMs in Nanometer Era" in IEICE TRANSACTIONS on Electronics,
vol. E90-C, no. 4, pp. 735-742, April 2007, doi: 10.1093/ietele/e90-c.4.735.
Abstract: Low-voltage nanometer-scale embedded RAM cells are described. First, low-voltage RAM cells are compared in terms of cell size, threshold voltage for MOS transistor, and signal charge. Second, the solution for 6T and 4T SRAM cells to widen the voltage margin are investigated, especially the advantages with a back-gate controlled thin buried-oxide fully-depleted (FD) SOI are presented. Then, DRAM approach with a novel twin-cell is discussed in terms of improving the retention time and low-voltage operation. These low-voltage cell technologies are the promising candidates for future embedded RAMs.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e90-c.4.735/_p
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@ARTICLE{e90-c_4_735,
author={Takayuki KAWAHARA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Low-Voltage Embedded RAMs in Nanometer Era},
year={2007},
volume={E90-C},
number={4},
pages={735-742},
abstract={Low-voltage nanometer-scale embedded RAM cells are described. First, low-voltage RAM cells are compared in terms of cell size, threshold voltage for MOS transistor, and signal charge. Second, the solution for 6T and 4T SRAM cells to widen the voltage margin are investigated, especially the advantages with a back-gate controlled thin buried-oxide fully-depleted (FD) SOI are presented. Then, DRAM approach with a novel twin-cell is discussed in terms of improving the retention time and low-voltage operation. These low-voltage cell technologies are the promising candidates for future embedded RAMs.},
keywords={},
doi={10.1093/ietele/e90-c.4.735},
ISSN={1745-1353},
month={April},}
Copy
TY - JOUR
TI - Low-Voltage Embedded RAMs in Nanometer Era
T2 - IEICE TRANSACTIONS on Electronics
SP - 735
EP - 742
AU - Takayuki KAWAHARA
PY - 2007
DO - 10.1093/ietele/e90-c.4.735
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E90-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2007
AB - Low-voltage nanometer-scale embedded RAM cells are described. First, low-voltage RAM cells are compared in terms of cell size, threshold voltage for MOS transistor, and signal charge. Second, the solution for 6T and 4T SRAM cells to widen the voltage margin are investigated, especially the advantages with a back-gate controlled thin buried-oxide fully-depleted (FD) SOI are presented. Then, DRAM approach with a novel twin-cell is discussed in terms of improving the retention time and low-voltage operation. These low-voltage cell technologies are the promising candidates for future embedded RAMs.
ER -
English
