We evaluated soft-error tolerance by heavy-ion irradiation test on three-types of flip-flops (FFs) named the standard FF (STDFF), the dual feedback recovery FF (DFRFF), and the DFRFF with long delay (DFRFFLD) in 22 and 65 nm fully-depleted silicon on insulator (FD-SOI) technologies. The guard-gate (GG) structure in DFRFF mitigates soft errors. A single event transient (SET) pulse is removed by the C-element with the signal delayed by the GG structure. DFRFFLD increases the GG delay by adding two more inverters as delay elements. We investigated the effectiveness of the GG structure in 22 and 65 nm. In 22 nm, Kr (40.3 MeV-cm2/mg) and Xe (67.2 MeV-cm2/mg) irradiation tests revealed that DFRFFLD has sufficient soft-error tolerance in outer space. In 65 nm, the relationship between GG delay and CS reveals the GG delay time which no error was observed under Kr irradiation.

A temperature-variation-tolerant intermittent startup circuit (ISC) that suppresses quiescent current to 300nA at 0.48V was developed. The ISC is a key circuit for a batteryless wireless sensor that can detect a 1μA generation current of energy harvesting sources from the intervals of wireless signals. The ISC consists of an ultralow-voltage detector composed of a depletion-type MOSFET and low-Vth MOSFETs, a Dickson-type gate-boosted charge pump circuit, and a power-switch control circuit. The detector consists of a voltage reference comparator and a feedback-controlled latch circuit for a hysteresis function. The voltage reference comparator, which has a common source stage with a folded constant-current-source load composed of a depletion-type nMOSFET, makes it possible to reduce the temperature dependency of the detection voltage, while suppressing the quiescent current to 300nA at 0.48V. The ISC fabricated with fully-depleted silicon-on-insulator (FD-SOI) CMOS technology also suppresses the variation of the quiescent current. To verify the effectiveness of the circuit, the ISC was fabricated in a 0.8-μm triple-Vth FD-SOI CMOS process. An experiment on the fabricated system, the ISC boosts the input voltage of 0.48V to 2.4V while suppressing the quiescent current to less than 300nA at 0.48V. The measured temperature coefficient of the detection voltage was ±50ppm/°C. The fluctuation of the quiescent current was 250nA ± 90nA in the temperature range from 0°C to 40°C. An intermittent energy harvesting sensor with the ISC was also fabricated. The sensor could detect a generation current of 1μA at EH sources within an accuracy of ±15% in the temperature range from 0°C to 40°C. It was also successfully applied to a self-powered wireless plant-monitoring sensor system.

This paper presents a low-power and low-voltage 64-kb 8T three-port image memory using 28-nm FD-SOI process technology. Our proposed SRAM accommodates eight-transistor bit cells comprising one-write/two-read ports and a majority logic circuit to save active energy. The test chip operates at a supply voltage of 0.46V and access time of 140ns. The minimum energy point is a supply voltage of 0.54V and an access time of 55ns (= 18.2MHz), at which 484fJ/cycle in a write operation and 650fJ/cycle in a read operation are achieved assisted by majority logic. These factors are 69% and 47% smaller than those in a conventional 6T SRAM using the 28-nm FD-SOI process technology.

Cache memories are the major application of high-speed SRAMs, and they are frequently installed in high performance logic VLSIs including microprocessors. This paper presents a 4-way set-associative, SOI cache-tag memory. To obtain higher operating speed with less power dissipation, we devised an I/O-separated memory cell with a dual-rail wordline, which is used to transmit complementary selection signals. The address decoding delay was shortened using CMOS dual-rail logic. To enhance the maximum operating frequency, bitline's recovery operations after writing data were eliminated using a memory array configuration without half-selected cells. Moreover, conventional, sensitive but slow differential amplifiers were successfully removed from the data I/O circuitry with a hierarchical bitline scheme. As regards the stored data management, we devised a new hardware-oriented LRU-data replacement algorithm on the basis of 6-bit directed graph. With the experimental results obtained with a test chip fabricated with a 0.25-µm CMOS/SIMOX process, the core of the cache-tag memory with a 1024-set configuration can achieve a 1.5-ns address access time under typical conditions of a 2-V power supply and 25°C. The power dissipation during standby was less than 14 µW, and that at the 500-MHz operation was 13-83 mW, depending on the bit-stream data pattern.

We propose a novel substrate-bias control scheme for an FD-SOI SRAM that suppresses inter-die variability. The proposed circuits detect inter-die threshold-voltage variation automatically, and then maximize read/write margins of memory cells to supply the substrate bias. We confirmed that a 486-kb 6T SRAM operates at 0.42 V, in which an FS corner can be compared as much as 0.14 V or more.

We have been developing low power cryogenic readout electronics for space borne large format far-infrared image sensors. As the circuit elements, a fully-depleted-silicon-on-insulator (FD-SOI) CMOS process was adopted because they keep good static performance even at 4.2 K where where various anomalous behaviors are seen for other types of CMOS transistors. We have designed and fabricated several test circuits with the FD-SOI CMOS process and confirmed that an operational amplifier successfully works with an open loop gain over 1000 and with a power consumption around 1.3 µW as designed, and the basic digital circuits worked well. These results prove that the FD-SOI CMOS process is a promising candidate of the ideal cryogenic readout electronics for far-infrared astronomical focal plane array sensors.

The minimum operating voltage, Vmin, of nanoscale CMOS LSIs is investigated to breach the 1-V wall that we are facing in the 65-nm device generation, and open the door to the below 0.5-V era. A new method using speed variation is proposed to evaluate Vmin. It shows that Vmin is very sensitive to the lowest necessary threshold voltage, Vt0, of MOSFETs and to threshold-voltage variations, Δ Vt, which become more significant with device scaling. There is thus a need for low-Vt0 circuits and ΔVt-immune MOSFETs to reduce Vmin. For memory-rich LSIs, the SRAM block is particularly problematic because it has the highest Vmin. Various techniques are thus proposed to reduce the Vmin: using RAM repair, shortening the data line, up-sizing, and using more relaxed MOSFET scaling. To effectively reduce Vmin of other circuit blocks, dual-Vt0 and dual-VDD circuits using gate-source reverse biasing, temporary activation, and series connection of another small low-Vt0 MOSFET are proposed. They are dynamic logic circuits enabling the power-delay product of the conventional static CMOS inverter to be reduced to 0.09 at a 0.2-V supply, and a DRAM dynamic sense amplifier and power switches operable at below 0.5 V. In addition, a fully-depleted structure (FD-SOI) and fin-type structure (FinFET) for ΔVt-immune MOSFETs are discussed in terms of their low-voltage potential and challenges. As a result, the height up-scalable FinFETs turns out to be quite effective to reduce Vmin to less than 0.5 V, if combined with the low-Vt0 circuits. For mixed-signal LSIs, investigation of low-voltage potential of analog circuits, especially for comparators and operational amplifiers, reveals that simple inverter op-amps, in which the low gain and nonlinearity are compensated for by digitally assisted analog designs, are crucial to 0.5-V operations. Finally, it is emphasized that the development of relevant devices and fabrication processes is the key to the achievement of 0.5-V nanoscale LSIs.

Low-voltage nanometer-scale embedded RAM cells are described. First, low-voltage RAM cells are compared in terms of cell size, threshold voltage for MOS transistor, and signal charge. Second, the solution for 6T and 4T SRAM cells to widen the voltage margin are investigated, especially the advantages with a back-gate controlled thin buried-oxide fully-depleted (FD) SOI are presented. Then, DRAM approach with a novel twin-cell is discussed in terms of improving the retention time and low-voltage operation. These low-voltage cell technologies are the promising candidates for future embedded RAMs.

We propose a design methodology of a low-voltage CMOS low-noise amplifier (LNA) consisting of a common-source and a common-gate stages. We first derive equations of power gain, noise figure (NF) and input third-order intercept point (IIP3) of the two-stage LNA. A design methodology of the LNA is presented by using graphs based on analytical equations. A 1-V 5.4-GHz LNA was implemented in 0.15-µm fully-depleted silicon-on-insulator (FD-SOI) CMOS technology. Measurement results show a power gain of 23 dB, NF of 1.7 dB and IIP3 of -6.1 dBm with a power consumption of 8.3 mW. These measured results are consistent with calculated results, which ensures the validity of the derived equations and the proposed design methodology.

A new small-signal model for fully depleted silicon-on-insulator (FD-SOI) MOSFETs operating at RF frequencies is presented. The model accounts for the non-quasi-static effect by determining model parameters using a curve fitting procedure to reproduce the frequency response of FD-SOI MOSFETs. The accuracy of the model is validated by comparison of S parameters with measured results in the range from 0.2 GHz to 20 GHz.

A cyclic A/D conversion circuit technique for sensor networks has been developed using 0.2-µm CMOS/FD-SOI technology. The FD-SOI analog switches can lower the supply voltage without degrading accuracy because of their negligible body effect. The proposed A/D converter achieves operation at the supply voltage of 1 V or less and can handle a sampling frequency ranging from 8 Sps to 8 kSps with a new clocking technique.

The threshold voltage mismatch of FD (Fully depleted) SOI (Silicon on insulator) devices have been studied. Floating body MOSFETs operating at high drain voltage show a large mismatch in the threshold voltage compared with body-tied MOSFETs. Those experimental data under different drain voltages indicate that both floating body effect and DIBL (Drain induced barrier lowering) are involved in the threshold voltage mismatch of floating body MOSFETs.