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Development of Cryogenic Readout Electronics for Far-Infrared Astronomical Focal Plane Array
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We have been developing low power cryogenic readout electronics for space borne large format far-infrared image sensors. As the circuit elements, a fully-depleted-silicon-on-insulator (FD-SOI) CMOS process was adopted because they keep good static performance even at 4.2 K where where various anomalous behaviors are seen for other types of CMOS transistors. We have designed and fabricated several test circuits with the FD-SOI CMOS process and confirmed that an operational amplifier successfully works with an open loop gain over 1000 and with a power consumption around 1.3 µW as designed, and the basic digital circuits worked well. These results prove that the FD-SOI CMOS process is a promising candidate of the ideal cryogenic readout electronics for far-infrared astronomical focal plane array sensors.
- Publication
- IEICE TRANSACTIONS on Communications Vol.E94-B No.11 pp.2952-2960
- Publication Date
- 2011/11/01
- Publicized
- Online ISSN
- 1745-1345
- DOI
- 10.1587/transcom.E94.B.2952
- Type of Manuscript
- Special Section INVITED PAPER (Special Section on Space, Aeronautical and Navigational Technologies in Conjunction with Main Topics of WSANE and ICSANE)
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Hirohisa NAGATA, Takehiko WADA, Hirokazu IKEDA, Yasuo ARAI, Morifumi OHNO, Koichi NAGASE, "Development of Cryogenic Readout Electronics for Far-Infrared Astronomical Focal Plane Array" in IEICE TRANSACTIONS on Communications,
vol. E94-B, no. 11, pp. 2952-2960, November 2011, doi: 10.1587/transcom.E94.B.2952.
Abstract: We have been developing low power cryogenic readout electronics for space borne large format far-infrared image sensors. As the circuit elements, a fully-depleted-silicon-on-insulator (FD-SOI) CMOS process was adopted because they keep good static performance even at 4.2 K where where various anomalous behaviors are seen for other types of CMOS transistors. We have designed and fabricated several test circuits with the FD-SOI CMOS process and confirmed that an operational amplifier successfully works with an open loop gain over 1000 and with a power consumption around 1.3 µW as designed, and the basic digital circuits worked well. These results prove that the FD-SOI CMOS process is a promising candidate of the ideal cryogenic readout electronics for far-infrared astronomical focal plane array sensors.
URL: https://global.ieice.org/en_transactions/communications/10.1587/transcom.E94.B.2952/_p
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@ARTICLE{e94-b_11_2952,
author={Hirohisa NAGATA, Takehiko WADA, Hirokazu IKEDA, Yasuo ARAI, Morifumi OHNO, Koichi NAGASE, },
journal={IEICE TRANSACTIONS on Communications},
title={Development of Cryogenic Readout Electronics for Far-Infrared Astronomical Focal Plane Array},
year={2011},
volume={E94-B},
number={11},
pages={2952-2960},
abstract={We have been developing low power cryogenic readout electronics for space borne large format far-infrared image sensors. As the circuit elements, a fully-depleted-silicon-on-insulator (FD-SOI) CMOS process was adopted because they keep good static performance even at 4.2 K where where various anomalous behaviors are seen for other types of CMOS transistors. We have designed and fabricated several test circuits with the FD-SOI CMOS process and confirmed that an operational amplifier successfully works with an open loop gain over 1000 and with a power consumption around 1.3 µW as designed, and the basic digital circuits worked well. These results prove that the FD-SOI CMOS process is a promising candidate of the ideal cryogenic readout electronics for far-infrared astronomical focal plane array sensors.},
keywords={},
doi={10.1587/transcom.E94.B.2952},
ISSN={1745-1345},
month={November},}
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TY - JOUR
TI - Development of Cryogenic Readout Electronics for Far-Infrared Astronomical Focal Plane Array
T2 - IEICE TRANSACTIONS on Communications
SP - 2952
EP - 2960
AU - Hirohisa NAGATA
AU - Takehiko WADA
AU - Hirokazu IKEDA
AU - Yasuo ARAI
AU - Morifumi OHNO
AU - Koichi NAGASE
PY - 2011
DO - 10.1587/transcom.E94.B.2952
JO - IEICE TRANSACTIONS on Communications
SN - 1745-1345
VL - E94-B
IS - 11
JA - IEICE TRANSACTIONS on Communications
Y1 - November 2011
AB - We have been developing low power cryogenic readout electronics for space borne large format far-infrared image sensors. As the circuit elements, a fully-depleted-silicon-on-insulator (FD-SOI) CMOS process was adopted because they keep good static performance even at 4.2 K where where various anomalous behaviors are seen for other types of CMOS transistors. We have designed and fabricated several test circuits with the FD-SOI CMOS process and confirmed that an operational amplifier successfully works with an open loop gain over 1000 and with a power consumption around 1.3 µW as designed, and the basic digital circuits worked well. These results prove that the FD-SOI CMOS process is a promising candidate of the ideal cryogenic readout electronics for far-infrared astronomical focal plane array sensors.
ER -
English
