IEICE TRANSACTIONS on Electronics
A 28-nm 484-fJ/writecycle 650-fJ/readcycle 8T Three-Port FD-SOI SRAM for Image Processor
Summary :
This paper presents a low-power and low-voltage 64-kb 8T three-port image memory using 28-nm FD-SOI process technology. Our proposed SRAM accommodates eight-transistor bit cells comprising one-write/two-read ports and a majority logic circuit to save active energy. The test chip operates at a supply voltage of 0.46V and access time of 140ns. The minimum energy point is a supply voltage of 0.54V and an access time of 55ns (= 18.2MHz), at which 484fJ/cycle in a write operation and 650fJ/cycle in a read operation are achieved assisted by majority logic. These factors are 69% and 47% smaller than those in a conventional 6T SRAM using the 28-nm FD-SOI process technology.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E99-C No.8 pp.901-908
- Publication Date
- 2016/08/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E99.C.901
- Type of Manuscript
- Special Section PAPER (Special Section on Low-Power and High-Speed Chips)
- Category
Authors
Haruki MORI
Kobe University
Yohei UMEKI
Kobe University
Shusuke YOSHIMOTO
Kobe University
Shintaro IZUMI
Kobe University
Koji NII
Renesas Electronics Corporation,Kanazawa University
Hiroshi KAWAGUCHI
Kobe University
Masahiko YOSHIMOTO
Kobe University
Keyword
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Haruki MORI, Yohei UMEKI, Shusuke YOSHIMOTO, Shintaro IZUMI, Koji NII, Hiroshi KAWAGUCHI, Masahiko YOSHIMOTO, "A 28-nm 484-fJ/writecycle 650-fJ/readcycle 8T Three-Port FD-SOI SRAM for Image Processor" in IEICE TRANSACTIONS on Electronics,
vol. E99-C, no. 8, pp. 901-908, August 2016, doi: 10.1587/transele.E99.C.901.
Abstract: This paper presents a low-power and low-voltage 64-kb 8T three-port image memory using 28-nm FD-SOI process technology. Our proposed SRAM accommodates eight-transistor bit cells comprising one-write/two-read ports and a majority logic circuit to save active energy. The test chip operates at a supply voltage of 0.46V and access time of 140ns. The minimum energy point is a supply voltage of 0.54V and an access time of 55ns (= 18.2MHz), at which 484fJ/cycle in a write operation and 650fJ/cycle in a read operation are achieved assisted by majority logic. These factors are 69% and 47% smaller than those in a conventional 6T SRAM using the 28-nm FD-SOI process technology.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E99.C.901/_p
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@ARTICLE{e99-c_8_901,
author={Haruki MORI, Yohei UMEKI, Shusuke YOSHIMOTO, Shintaro IZUMI, Koji NII, Hiroshi KAWAGUCHI, Masahiko YOSHIMOTO, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 28-nm 484-fJ/writecycle 650-fJ/readcycle 8T Three-Port FD-SOI SRAM for Image Processor},
year={2016},
volume={E99-C},
number={8},
pages={901-908},
abstract={This paper presents a low-power and low-voltage 64-kb 8T three-port image memory using 28-nm FD-SOI process technology. Our proposed SRAM accommodates eight-transistor bit cells comprising one-write/two-read ports and a majority logic circuit to save active energy. The test chip operates at a supply voltage of 0.46V and access time of 140ns. The minimum energy point is a supply voltage of 0.54V and an access time of 55ns (= 18.2MHz), at which 484fJ/cycle in a write operation and 650fJ/cycle in a read operation are achieved assisted by majority logic. These factors are 69% and 47% smaller than those in a conventional 6T SRAM using the 28-nm FD-SOI process technology.},
keywords={},
doi={10.1587/transele.E99.C.901},
ISSN={1745-1353},
month={August},}
Copy
TY - JOUR
TI - A 28-nm 484-fJ/writecycle 650-fJ/readcycle 8T Three-Port FD-SOI SRAM for Image Processor
T2 - IEICE TRANSACTIONS on Electronics
SP - 901
EP - 908
AU - Haruki MORI
AU - Yohei UMEKI
AU - Shusuke YOSHIMOTO
AU - Shintaro IZUMI
AU - Koji NII
AU - Hiroshi KAWAGUCHI
AU - Masahiko YOSHIMOTO
PY - 2016
DO - 10.1587/transele.E99.C.901
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E99-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 2016
AB - This paper presents a low-power and low-voltage 64-kb 8T three-port image memory using 28-nm FD-SOI process technology. Our proposed SRAM accommodates eight-transistor bit cells comprising one-write/two-read ports and a majority logic circuit to save active energy. The test chip operates at a supply voltage of 0.46V and access time of 140ns. The minimum energy point is a supply voltage of 0.54V and an access time of 55ns (= 18.2MHz), at which 484fJ/cycle in a write operation and 650fJ/cycle in a read operation are achieved assisted by majority logic. These factors are 69% and 47% smaller than those in a conventional 6T SRAM using the 28-nm FD-SOI process technology.
ER -
English
