In order to keep up with the growing need for memory bandwidth at low cost, a new synchronous DRAM (SDRAM) architecture is proposed. The SDRAM has programmable latency, burst length, and burst type for wide variety of applications. The experimental 16M SDRAM (2M8) achieves a 125-Mbyte/s data rate using 0.5-µm twin well CMOS technology.

Wide-voltage-range DRAM's with extended data retention are desirable for battery-operated or portable computers and consumer devices. This paper describes the techniques required to obtain wide operation, functionality, and performance of standard DRAM's from 1.8 V (2 NiCd or Alkaline batteries) to 3.6 V (upper end of LVTTL standard). Specific techniques shown are: 1) a low-power and low-voltage reference generator for detecting VCC level; 2) compensation of dc generators, VBB and VPP, for obtaining high speed at reduced voltages; 3) a static word-line driver and latch-isolation sense amplifier for reducing operating current; and 4) a programmable VCC variable self-refresh scheme for obtaining maximum data retention time over a full operating range. A sub-50-ns access time is obtained for a 16M DRAM(2M 8) by simulation.

This paper presents novel temperature-compensation circuit techniques for the CMOS DRAM internal voltage converter, the RC-delay circuit, and the back-bias generator, which do not need any additional process steps. The abovementioned circuits have been designed and evaluated through a 16-Mb CMOS DRAM. These circuits have shown an internal voltage converter (IVC) with an internal voltage temperature coefficient of 185 ppm/, and an RC-delay circuit with a delay time temperature coefficient of 0.03%/. As a result, 6.5-ns faster RAS access time and improved latch-up immunity have been achieved, compared with conventional circuit techniques.