Wide-voltage-range DRAM's with extended data retention are desirable for battery-operated or portable computers and consumer devices. This paper describes the techniques required to obtain wide operation, functionality, and performance of standard DRAM's from 1.8 V (2 NiCd or Alkaline batteries) to 3.6 V (upper end of LVTTL standard). Specific techniques shown are: 1) a low-power and low-voltage reference generator for detecting VCC level; 2) compensation of dc generators, VBB and VPP, for obtaining high speed at reduced voltages; 3) a static word-line driver and latch-isolation sense amplifier for reducing operating current; and 4) a programmable VCC variable self-refresh scheme for obtaining maximum data retention time over a full operating range. A sub-50-ns access time is obtained for a 16M DRAM(2M 8) by simulation.

This work describes an 8b 200 MHz time-interleaved subranging analog-to-digital converter (ADC) based on a single-poly digital CMOS process. Two fine ADCs for lower digital bits of the proposed ADC employ a time-sharing double- channel architecture to increase the sampling speed and a new reference voltage switching scheme to reduce the settling time of the reference voltages and the chip area. The proposed intermeshed resistor string, which generates reference voltages for fine ADCs, improves the linearity and the settling time of the reference voltages simultaneously. The proposed sample-and-hold amplifier employs an input dynamic common mode feedback circuit for high dynamic performance, based on conventional common-drain amplifiers and passive differential circuits.

In this work, a CMOS on-chip current reference circuit for memory, operational amplifiers, comparators, and data converters is proposed. The reference current is nearly insensitive to temperature and supply-voltage variations. In the proposed circuit, the current component with a positive temperature coefficient cancels that with a negative temperature coefficient each other. While conventional current reference circuits are based on bipolar transistors in BiCMOS, bipolar, or CMOS processes, the proposed circuit can be integrated on a single chip with other digital and analog circuits using a standard CMOS process and extra masks are not required. Measured results are demonstrated for two different prototypes. The first is fabricated employing a 1.0 µm p-well double-poly double-metal CMOS process and operates at 5 V nominally. The second, based on a 0.6 µm n-well process, is optimized for 3 V to 5 V operation. The latter prototype achieves the temperature coefficient of 98 ppm/ over a temperature range from -25 to 75 and the output variation of 1.5% with the supply-voltage changes from 2.5 V to 5.5 V. A simple calibration technique for reducing output current variations improves circuit yield.

This work proposes a 10 b 200 MS/s 1.8 mm2 83 mW 0.13 µm CMOS ADC based on highly linear integrated capacitors for high-quality video system applications such as next-generation DTV and radar vision and wireless communication system applications such as WLAN, WiMax, SDR, LMDS, and MMDS simultaneously requiring low voltage, low power, and small area at high speed. The proposed 3-stage pipeline ADC optimizes chip area and power dissipation at the target resolution and sampling rate. The proposed ADC employs two versions of the SHA with gate-bootstrapped NMOS switches and conventional CMOS switches to verify and compare the input sampling effectiveness. Both of the two versions of the wide-band low-noise SHA maintain 10 b input accuracy at 200 MS/s. The proposed all signal-isolated 3-D completely symmetric capacitor layout reduces the device mismatch of two MDACs by isolating each unit capacitor from all neighboring signal lines with all the employed metal lines and by placing extra internal metal lines with a fixed internal bias voltage between signal lines connecting the bottom plate of each unit capacitor. The low-noise on-chip current and voltage references with internal RC filters can select optional off-chip voltage references. The prototype ADC is implemented in a 0.13 µm 1P8M CMOS process. The measured DNL and INL are within 0.24 LSB and 0.35 LSB while the ADC shows a maximum SNDR of 54 dB and 48 dB and a maximum SFDR of 67 dB and 61 dB at 200 MS/s and 250 MS/s, respectively. The ADC with an active die area of 1.8 mm2 consumes 83 mW at 200 MS/s and at a 1.2 V supply.

This work describes an 8b 240 MS/s CMOS ADC as one of embedded core circuits for high-performance displays based on low-noise on-chip references and dual-mode inputs with the requirements of limited pins, low power, and small size at high speed. The proposed ADC uses externally connected pins only for analog inputs, digital outputs, and supplies. The ADC employs (1) a two-step pipeline architecture to optimize power and chip size at the target sampling frequency of 240 MHz, (2) advanced bootstrapping techniques to achieve high signal bandwidth in the input SHA, and (3) RC filter-based on-chip current and voltage references to improve noise performance with a power-off function for portable applications. The prototype ADC is implemented in a 0.18 µm CMOS and simultaneously integrated in a DVD system with dual-mode inputs. The prototype ADC shows the measured DNL and INL within 0.49LSB and 0.69LSB, and the SNDR and SFDR exceeding 38 dB and 50 dB for inputs up to the Nyquist frequency at 240 MS/s. The ADC consumes 104 mW at 240 MS/s and an active die area is 1.36 mm2 .

This work describes a 12-bit 100 MS/s 0.13 µm CMOS ADC for 3G wireless communication systems such as two-carrier W-CDMA applications. The proposed ADC employs a four-step pipeline architecture to optimize power consumption and chip area at the target resolution and sampling rate. Area-efficient gate-bootstrapped sampling switches of the input SHA maintain high signal linearity over the Nyquist rate even at a 1.0 V supply. The cascode compensation using a low-impedance feedback path in two-stage amplifiers of the SHA and MDACs achieves the required conversion speed and phase margin with less power consumption and area compared to the Miller compensation. A low-glitch dynamic latch in the sub-ranging flash ADCs reduces kickback noise referred to the input of comparator by isolating the pre-amplifier from the regeneration latch output. The proposed on-chip current and voltage references are based on triple negative TC circuits. The prototype ADC in a 0.13 µm 1P8M CMOS technology demonstrates the measured DNL and INL within 0.38LSB and 0.96LSB at 12-bit, respectively. The ADC shows a maximum SNDR and SFDR of 64.5 dB and 78.0 dB at 100 MS/s, respectively. The ADC with an active die area of 1.22 mm2 consumes 42.0 mW at 100 MS/s and a 1.2 V supply, corresponding to a figure-of-merit of 0.31 pJ/conversion-step.

This work describes a 12 b 200 kS/s 0.52 mA 0.47 mm2 ADC for sensor applications such as motor control, 3-phase power control, and CMOS image sensors simultaneously requiring ultra-low power and small size. The proposed ADC is based on the conventional algorithmic architecture with a recycling signal path to optimize sampling rate, resolution, chip area, and power consumption. The input SHA with eight input channels employs a folded-cascode amplifier to achieve a required DC gain and a high phase margin. A 3-D fully symmetric layout with critical signal lines shielded reduces the capacitor and device mismatch of the multiplying D/A converter while switched-bias power-reduction circuits minimize the power consumption of analog amplifiers. Current and voltage references are integrated on chip with optional off-chip voltage references for low glitch noise. The down-sampling clock signal selects the sampling rate of 200 kS/s and 10 kS/s with a further reduced power depending on applications. The prototype ADC in a 0.18 µm n-well 1P6M CMOS process demonstrates a maximum measured DNL and INL within 0.40 LSB and 1.97 LSB and shows a maximum SNDR and SFDR of 55 dB and 70 dB at all sampling frequencies up to 200 kS/s, respectively. The ADC occupies an active die area of 0.47 mm2 and consumes 0.94 mW at 200 kS/s and 0.63 mW at 10 kS/s with a 1.8 V supply.

This work proposes an 8b 220 MS/s 230 mW 3-stage pipeline CMOS ADC with on-chip filters for temperature- and power supply- insensitive voltage references. The proposed RC low-pass filters reduce reference settling time at heavy R&C loads and improve switching noise performance without conventional off-chip bypass capacitors. The prototype ADC fabricated in a 0.25 µm CMOS occupies the active die area of 2.25 mm2 and shows the measured DNL and INL of maximum 0.43 LSB and 0.82 LSB, respectively. The ADC maintains the SNDR of 43 dB and 41 dB up to the 110 MHz input at 200 MS/s and 220 MS/s, respectively, while the SNDR at the 500 MHz input is degraded as much as only 3 dB than the SNDR at the 110 MHz input.

This paper describes a switched-capacitor type DC-DC up converter with high efficiency and low-ripple voltage. Identical charge pumps operating sequentially in the proposed DC-DC converter reduce the magnitude of the ripple voltage to 20% of the conventional converters. A new charge pump adopting PMOS switches near the output stage improves the power efficiency of the DC-DC converter by 10%. The proposed DC-DC converter is applied, as a test vehicle, to a phase-locked loop circuit which is sensitive to power supply noise. All circuits are fabricated and measured in a 0.65-µm CMOS process.

This work describes a 12-bit 100 MS/s 0.13 µm CMOS three-stage pipeline ADC with various circuit design techniques to reduce power and die area. Digitally controlled timing delay and gate-bootstrapping circuits improve the linearity and sampling time mismatch of the SHA-free input network composed of an MDAC and a FLASH ADC. A single two-stage switched op-amp is shared between adjacent MDACs without MOS series switches and memory effects by employing two separate NMOS input pairs based on slightly overlapped switching clocks. The interpolation, open-loop offset sampling, and two-step reference selection schemes for a back-end 6-bit flash ADC reduce both power consumption and chip area drastically compared to the conventional 6-bit flash ADCs. The prototype ADC in a 0.13 µm CMOS process demonstrates measured differential and integral non-linearities within 0.44LSB and 1.54LSB, respectively. The ADC shows a maximum SNDR and SFDR of 60.5 dB and 71.2 dB at 100 MS/s, respectively. The ADC with an active die area of 0.92 mm2 consumes 19 mW at 100 MS/s from a 1.0 V supply. The measured FOM is 0.22 pJ/conversion-step.

This paper describes an 8b 52 MHz CMOS subranging analog-to-digital converter (ADC) for digital subscriber loop applications. The proposed ADC based on an improved time-interleaved architecture removes the holding time which is typically observed in the conventional double-channel subranging ADC's to increase the throughput rate by 50%. The ADC employs the interpolation technique in the back-end subranging ADC's for residue signal processing to minimize the active die area and the power consumption. A layout technique is adopted to reduce the plasma-induced comparator offsets and the die area of the ADC. The fabricated and measured prototype ADC in a 0.8 µm CMOS process shows nonlinearities less than 0.4 LSB and the signal-to-noise-and-distortion ratio of 43 dB for a 1 MHz input at a 52 MHz sampling rate with 230 mW.

This paper proposes resolution enhancement techniques for high-speed multi-stage pipelined analog-to-digital converters (ADC's) based on a multi-bit/stage multiplying digital-to-analog converter. The proposed techniques increase ADC resolution and simultaneously minimize chip area, power dissipation, and circuit complexity by removing the gain-proration procedure, which is required in conventional digitally calibrated multi-stage ADC's to reduce unavoidable gain errors between stages with more than two stages calibrated. The resolution of the proposed ADC can be extended furthermore by combining a conventional commutated feedback-capacitor switching scheme with the digital-domain self calibration.

This work proposes a 10b 100 MS/s 1.4 mm2 CMOS ADC for low-power multimedia applications. The proposed two-step pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The wide-band SHA employs a gate-bootstrapping circuit to handle both single-ended and differential inputs of 1.2 Vp-p at 10b accuracy while the second-stage flash ADC employs open-loop offset sampling techniques to achieve 6b resolution. A 3-D fully symmetrical layout reduces the capacitor and device mismatch of the first-stage MDAC. The low-noise references are integrated on chip with optional off-chip voltage references. The prototype 10b ADC implemented in a 0.18 µm CMOS shows the maximum measured DNL and INL of 0.59LSB and 0.77LSB, respectively. The ADC demonstrates an SNDR of 53.7 dB, an SFDR of 61.5 dB, and the power dissipation of 56 mW at 100 MS/s.

In order to keep up with the growing need for memory bandwidth at low cost, a new synchronous DRAM (SDRAM) architecture is proposed. The SDRAM has programmable latency, burst length, and burst type for wide variety of applications. The experimental 16M SDRAM (2M8) achieves a 125-Mbyte/s data rate using 0.5-µm twin well CMOS technology.