IEICE TRANSACTIONS on Electronics
An 8b 220 MS/s 0.25 µm CMOS Pipeline ADC with On-Chip RC-Filter Based Voltage References
Summary :
This work proposes an 8b 220 MS/s 230 mW 3-stage pipeline CMOS ADC with on-chip filters for temperature- and power supply- insensitive voltage references. The proposed RC low-pass filters reduce reference settling time at heavy R&C loads and improve switching noise performance without conventional off-chip bypass capacitors. The prototype ADC fabricated in a 0.25 µm CMOS occupies the active die area of 2.25 mm2 and shows the measured DNL and INL of maximum 0.43 LSB and 0.82 LSB, respectively. The ADC maintains the SNDR of 43 dB and 41 dB up to the 110 MHz input at 200 MS/s and 220 MS/s, respectively, while the SNDR at the 500 MHz input is degraded as much as only 3 dB than the SNDR at the 110 MHz input.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E88-C No.4 pp.768-772
- Publication Date
- 2005/04/01
- Publicized
- Online ISSN
- DOI
- 10.1093/ietele/e88-c.4.768
- Type of Manuscript
- PAPER
- Category
- Electronic Circuits
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Young-Jae CHO, Hyuen-Hee BAE, Seung-Hoon LEE, "An 8b 220 MS/s 0.25 µm CMOS Pipeline ADC with On-Chip RC-Filter Based Voltage References" in IEICE TRANSACTIONS on Electronics,
vol. E88-C, no. 4, pp. 768-772, April 2005, doi: 10.1093/ietele/e88-c.4.768.
Abstract: This work proposes an 8b 220 MS/s 230 mW 3-stage pipeline CMOS ADC with on-chip filters for temperature- and power supply- insensitive voltage references. The proposed RC low-pass filters reduce reference settling time at heavy R&C loads and improve switching noise performance without conventional off-chip bypass capacitors. The prototype ADC fabricated in a 0.25 µm CMOS occupies the active die area of 2.25 mm2 and shows the measured DNL and INL of maximum 0.43 LSB and 0.82 LSB, respectively. The ADC maintains the SNDR of 43 dB and 41 dB up to the 110 MHz input at 200 MS/s and 220 MS/s, respectively, while the SNDR at the 500 MHz input is degraded as much as only 3 dB than the SNDR at the 110 MHz input.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e88-c.4.768/_p
Copy
@ARTICLE{e88-c_4_768,
author={Young-Jae CHO, Hyuen-Hee BAE, Seung-Hoon LEE, },
journal={IEICE TRANSACTIONS on Electronics},
title={An 8b 220 MS/s 0.25 µm CMOS Pipeline ADC with On-Chip RC-Filter Based Voltage References},
year={2005},
volume={E88-C},
number={4},
pages={768-772},
abstract={This work proposes an 8b 220 MS/s 230 mW 3-stage pipeline CMOS ADC with on-chip filters for temperature- and power supply- insensitive voltage references. The proposed RC low-pass filters reduce reference settling time at heavy R&C loads and improve switching noise performance without conventional off-chip bypass capacitors. The prototype ADC fabricated in a 0.25 µm CMOS occupies the active die area of 2.25 mm2 and shows the measured DNL and INL of maximum 0.43 LSB and 0.82 LSB, respectively. The ADC maintains the SNDR of 43 dB and 41 dB up to the 110 MHz input at 200 MS/s and 220 MS/s, respectively, while the SNDR at the 500 MHz input is degraded as much as only 3 dB than the SNDR at the 110 MHz input.},
keywords={},
doi={10.1093/ietele/e88-c.4.768},
ISSN={},
month={April},}
Copy
TY - JOUR
TI - An 8b 220 MS/s 0.25 µm CMOS Pipeline ADC with On-Chip RC-Filter Based Voltage References
T2 - IEICE TRANSACTIONS on Electronics
SP - 768
EP - 772
AU - Young-Jae CHO
AU - Hyuen-Hee BAE
AU - Seung-Hoon LEE
PY - 2005
DO - 10.1093/ietele/e88-c.4.768
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E88-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2005
AB - This work proposes an 8b 220 MS/s 230 mW 3-stage pipeline CMOS ADC with on-chip filters for temperature- and power supply- insensitive voltage references. The proposed RC low-pass filters reduce reference settling time at heavy R&C loads and improve switching noise performance without conventional off-chip bypass capacitors. The prototype ADC fabricated in a 0.25 µm CMOS occupies the active die area of 2.25 mm2 and shows the measured DNL and INL of maximum 0.43 LSB and 0.82 LSB, respectively. The ADC maintains the SNDR of 43 dB and 41 dB up to the 110 MHz input at 200 MS/s and 220 MS/s, respectively, while the SNDR at the 500 MHz input is degraded as much as only 3 dB than the SNDR at the 110 MHz input.
ER -
English
