IEICE TRANSACTIONS on Electronics
An 8b 200 MHz Time-Interleaved Subranging ADC Based on a Single-Poly Digital CMOS Process
Summary :
This work describes an 8b 200 MHz time-interleaved subranging analog-to-digital converter (ADC) based on a single-poly digital CMOS process. Two fine ADCs for lower digital bits of the proposed ADC employ a time-sharing double- channel architecture to increase the sampling speed and a new reference voltage switching scheme to reduce the settling time of the reference voltages and the chip area. The proposed intermeshed resistor string, which generates reference voltages for fine ADCs, improves the linearity and the settling time of the reference voltages simultaneously. The proposed sample-and-hold amplifier employs an input dynamic common mode feedback circuit for high dynamic performance, based on conventional common-drain amplifiers and passive differential circuits.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E86-C No.3 pp.506-513
- Publication Date
- 2003/03/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- PAPER
- Category
- Electronic Circuits
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Jung-Woong MOON, Seung-Hoon LEE, "An 8b 200 MHz Time-Interleaved Subranging ADC Based on a Single-Poly Digital CMOS Process" in IEICE TRANSACTIONS on Electronics,
vol. E86-C, no. 3, pp. 506-513, March 2003, doi: .
Abstract: This work describes an 8b 200 MHz time-interleaved subranging analog-to-digital converter (ADC) based on a single-poly digital CMOS process. Two fine ADCs for lower digital bits of the proposed ADC employ a time-sharing double- channel architecture to increase the sampling speed and a new reference voltage switching scheme to reduce the settling time of the reference voltages and the chip area. The proposed intermeshed resistor string, which generates reference voltages for fine ADCs, improves the linearity and the settling time of the reference voltages simultaneously. The proposed sample-and-hold amplifier employs an input dynamic common mode feedback circuit for high dynamic performance, based on conventional common-drain amplifiers and passive differential circuits.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e86-c_3_506/_p
Copy
@ARTICLE{e86-c_3_506,
author={Jung-Woong MOON, Seung-Hoon LEE, },
journal={IEICE TRANSACTIONS on Electronics},
title={An 8b 200 MHz Time-Interleaved Subranging ADC Based on a Single-Poly Digital CMOS Process},
year={2003},
volume={E86-C},
number={3},
pages={506-513},
abstract={This work describes an 8b 200 MHz time-interleaved subranging analog-to-digital converter (ADC) based on a single-poly digital CMOS process. Two fine ADCs for lower digital bits of the proposed ADC employ a time-sharing double- channel architecture to increase the sampling speed and a new reference voltage switching scheme to reduce the settling time of the reference voltages and the chip area. The proposed intermeshed resistor string, which generates reference voltages for fine ADCs, improves the linearity and the settling time of the reference voltages simultaneously. The proposed sample-and-hold amplifier employs an input dynamic common mode feedback circuit for high dynamic performance, based on conventional common-drain amplifiers and passive differential circuits.},
keywords={},
doi={},
ISSN={},
month={March},}
Copy
TY - JOUR
TI - An 8b 200 MHz Time-Interleaved Subranging ADC Based on a Single-Poly Digital CMOS Process
T2 - IEICE TRANSACTIONS on Electronics
SP - 506
EP - 513
AU - Jung-Woong MOON
AU - Seung-Hoon LEE
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E86-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 2003
AB - This work describes an 8b 200 MHz time-interleaved subranging analog-to-digital converter (ADC) based on a single-poly digital CMOS process. Two fine ADCs for lower digital bits of the proposed ADC employ a time-sharing double- channel architecture to increase the sampling speed and a new reference voltage switching scheme to reduce the settling time of the reference voltages and the chip area. The proposed intermeshed resistor string, which generates reference voltages for fine ADCs, improves the linearity and the settling time of the reference voltages simultaneously. The proposed sample-and-hold amplifier employs an input dynamic common mode feedback circuit for high dynamic performance, based on conventional common-drain amplifiers and passive differential circuits.
ER -
English
