A brief review is given on a crossover in transport between quantum and classical regimes due to the presence of inelastic scattering destroying the phase coherence. In the integer quantum Hall effect, the quantum regime corresponds to the edge-current picture and the classical to the bulk Hall current picture. The crossover between two regimes occurs through inelastic scattering. In a metallic carbon nanotube, there is a perfectly transmitting channel independent of energy for conventional scatterers having potential range larger than the lattice constant, making the nanotube a perfect conductor. When several bands coexist at the Fermi level, such a perfect channel is destroyed by inelastic scattering.

The implant-anneal cycle for B doping during Si device fabrication causes transient enhanced diffusion (TED) of B and the formation of small immobile B-interstitial clusters (BICs) which deactivate the B. Additionally, since modern ultrashallow devices put most of the B in immediate proximity of the Si/SiO₂ interface, interface-dopant interactions like segregation become increasingly important. In this work, we use density-functional theory calculations to study TED, clustering, and segregation of B during annealing and discuss a continuum model which combines the TED and clustering results.

In this work, we review our recent efforts to make effective use of atomistic calculations for the advancement of VLSI process simulation. We focus on three example applications: the behavior of implanted fluorine, arsenic diffusion and activation, and the impact of charge interactions on doping fluctuations.

Nowadays, silicon technologies with feature sizes around 100 nm are used in the microelectronics industry to produce gigabits integrated circuits. The prime part of numerical simulation in their development is now well established. One of the purpose of the numerical analyses is the improvement of the mechanical reliability. We synthetize in this paper various works we have performed on the macroscopical modeling and simulation of stress problems and their effects in silicon technologies.

An atomistic model for annealing simulation is presented. To well simulate both BED (Boron Enhanced Diffusion) and TED (Transient Enhanced Diffusion), the surface emission model, which describes the emission of point defects from surface during annealing, is implemented. The simulation is carried out for RTA annealing (1000 or 1050) after B implantation. The implantation energy varies from 0.5 keV to 13 keV. Agreements between simulation and SIMS data are achieved. Both BED and TED phenomena are characterized. The Enhancement of diffusion is discussed. The surface emission model is studied by simulation. The results shows that the surface emission has little effect on annealing of B 10 keV implantation while obvious effect on annealing of B 0.5 keV implantation. It indicates that the surface emission is much more necessary to simulate BED than TED.

New physical models, algorithms, and parameters are needed to accurately model emerging silicon-on-insulator (SOI) devices. The modeling approaches for various emerging SOI technologies are discussed in this paper.

The validity and capability of an iterative coupling scheme between single-particle frozen-field Monte Carlo simulations and nonlinear Poisson solutions for achieving self-consistency is investigated. For this purpose, a realistic 0.1 µm lightly-doped-drain (LDD) n-MOSFET with a maximum doping level of about 2.5 10²⁰ cm^-3 is simulated. It is found that taking the drift-diffusion (DD) or the hydrodynamic (HD) model as initial simulation leads to the same Monte Carlo result for the drain current. This shows that different electron densities taken either from a DD or a HD simulation in the bulk region, which is never visited by Monte Carlo electrons, have a negligible influence on the solution of the Poisson equation. For the device investigated about ten iterations are necessary to reach the stationary state after which gathering of cumulative averages can begin. Together with the absence of stability problems at high doping levels this makes the self-consistent single-particle approach (SPARTA) a robust and efficient method for the simulation of nanoscale MOSFETs where quasi-ballistic transport is crucial for the on-current.

In this work it is shown for the first time how to calculate in advance by momentum-based noise simulation for stationary Monte Carlo (MC) device simulations the CPU time, which is necessary to achieve a predefined error level. In addition, analytical expressions for the simulation-time factor of terminal current estimation are given. Without further improvements of the MC algorithm MC simulations of small terminal currents are found to be often prohibitively CPU intensive.

The validity of the expression for the electron energy flux is evaluated by using the Monte Carlo simulation. The drift, divergence, and scattering terms are directly calculated from changes in the physical values of particles. Each term composing the momentum and energy conservation equations can be reproduced by indirect calculation of the expression for the term that is a function of other physical values. However, it is found that a parameter in electron heat conductivity has to be adjusted to reproduce the direct calculation of the energy flux. Namely, the parameter of the Wiedemann-Franz law for heat conductivity should be chosen so that the underestimations of the drift and diffusion terms in the energy flux equation cancel each other. It is shown that the parameter influences the electron temperature in a 50-nm gate nMOSFET.

Though, high dielectric constant material is a possible near future solution in order to suppress gate current densities of MOSFETs, the barrier height generally decreases with an increasing dielectric constant. In this paper, the injection current through gate stacks has been calculated while taking into account the electron temperature using the W.K.B. method to understand the impact of the injection current from the drain edge.

Impact ionization and thermionic tunnelling as two possible breakdown mechanisms in scaled pseudomorphic high electron mobility transistors (PHEMTs) are investigated by Monte Carlo (MC) device simulations. Impact ionization is included in MC simulation as an additional scattering mechanism whereas thermionic tunnelling is treated in the WKB approximation during each time step in self-consistent MC simulation. Thermionic tunnelling starts at very low drain voltages but then quickly saturates. Therefore, it should not drastically affect the performance of scaled devices. Impact ionization threshold occurs at greater drain voltages which should assure a reasonable operation voltage scale for all scaled PHEMTs.

A new multi-phonon model for hydrogen desorption at Si/SiO₂ interface due to hot carriers is proposed for a multi-scale simulation, in which Lattice Monte Carlo method is coupled with Device Monte Carlo method by using a mediator-based common software platform. The power law between interface trap density and time (N_it t^α) of which power α =0.5 is demonstrated and shows good agreement with experimental results. Dependence of V_th shift on the current stress time is analyzed accurately by introducing an electron trap model. According to the multi-phonon mechanism, it is found that hot carriers will generate defects on the gate dielectrics in 13 nm gate device under low operation voltage of V_d=0.5 V but density of interface traps after long stress time is suppressed to 10¹⁵ m^-2.

Monte Carlo simulation of the low field electron mobility of strained Si and SiGe active layers on Si and SiGe substrates is considered. The Ge mole fractions of both the active layer and the substrate are varied in a wide range. The linear deformation potential theory is used to calculate the shifts of the conduction band minima due to uniaxial strain along [001]. The energy shifts and the effective masses are assumed to be functions of the Ge mole fraction. It is shown that in spite of the fact that the L-valleys remain degenerate under strain conditions considered here, they play an important role at very high Ge compositions especially when SiGe as substrate is used. We found that in this case the repopulation effects of the X-valleys affect electron mobility much stronger than the alloy scattering. We also generalize the ionized impurity scattering rate to include strain effects for doped materials and show that some of the important parameters such as effective density of states, inverse screening length, and the screening function are split due to strain and must be properly modified. Finally, we perform several simulations for undoped and doped materials using Si and SiGe substrates.

Electron transport in bulk Si and MOSFET inversion layers is studied using an ensemble Monte Carlo (EMC) technique coupled with the molecular dynamics (MD) method. The Coulomb interactions among point charges (electrons and negative ions) are directly taken into account in the simulation. It is demonstrated that the static screening of Coulomb interactions is correctly simulated by the EMC/MD method. Furthermore, we calculate the inversion layer mobility in Si MOSFETs, and mobility roll-off near the threshold voltage is observed by the present approach.

We describe progress we have achieved in the development of our quantum transport modeling for nano-scale devices. Our simulation is based upon either the non-equilibrium Green's function method (NEGF) or the quantum correction (QC) associated with density gradient method (DG) and/or effective potential method (EP). We show the results of our modeling methods applied to several devices and discuss issues faced with regards to computational time, open boundary conditions, and their relationship to self-consistent solution of the Poisson-NEGF equations. We also discuss those for efficiently tailored QC Monte Carlo techniques.

We use the Monte Carlo method to simulate electron transport in a zig-zag single-walled carbon nanotube with a wrapping index of n=10. Results show large low-field mobility, negative differential mobility, and large peaks in the drift velocity reaching 3.510⁷ cm/s.

The density gradient (DG) model is tested for its ability to describe tunneling currents through thin insulating barriers. Simulations of single barriers (MOS diodes, MOSFETs) and double barriers (RTDs) show the limitations of the DG model. For comparison, direct tunneling currents are calculated with the Schrodinger-Bardeen method and used as benchmark. The negative differential resistance (NDR) observed in simulating tunneling currents with the DG model turns out to be an artifact related to large density differences in the semiconductor regions. Such spurious NDR occurs both for single and double barriers and vanishes, if all semiconductor regions are equally doped.

A TCAD implementation of a quantum-mechanical mobility model in the commercial device simulator DESSIS__ISE is presented. The model makes use of an integrated 1D Schrodinger-Poisson solver. Effective mobilities µ_eff and transfer characteristics are calculated for DGSOI MOSFETs with a wide range of silicon film thickness t_Si and buried-oxide thickness t_box. It is shown that the volume-inversion related enhancement of µ_eff for t_Si 10 nm is bound to symmetrical DGSOIs, whereas SIMOX based devices with thick buried oxides limit µ_eff to the bulk value. The still immature technology makes a conclusive comparison with experimental data impossible.

A two-qubit system made of electrons running along coupled pairs of quantum wires is described and numerically analyzed. A brief review of the basic gates is given first, based on preliminary investigations, followed by the description of the electron dynamics. A detailed analysis of a conditional phase shifter is carried out by means of a time-dependent Schrodinger solver applied to a two-particle system. A quantum network suitable for creating entanglement is simulated, and results are shown. The physical structure of the proposed network is within the reach of a solid-state implementation. The physical parameters used in the computations have been chosen with reference to silicon quantum wires embedded in silicon dioxide.

Interactions between ESD protection devices and other components of a chip can lead to complex and not easily anticipated discharge bevahior. Triggering of a protection MOSFET is equivalent to the closing of a fast switch and can cause substantial transient discharge currents. The peak value of this current depends on the chip capacitance, resistance, properties of the protection clamp, etc. Careful optimization of the protection circuit is therefore necessary to avoid current overstress and circuit failure.

The potential drop and the self-heating due to the contact resistance at the interface between silicide and silicon are incorporated in the device simulation for ESD protection devices. A transition region is provided at the interface and the resistivity is calculated by scaling the contact resistance by the length of the region. The power density used in the heat conductive equation is calculated by using the potential drop and the contact resistance in the transition region. The validity of the present approach is checked by the Monte Carlo simulations. Using the technique, influence of the contact resistance on self-heating in an ESD protection device with the grounded gate MOSFET structure is simulated.

A realistic 3-D process/device simulation method was developed for investigating the fluctuation in device characteristics induced by the statistical nature of the number and position of discrete dopant atoms. Monte Carlo procedures are applied for both ion implantation and dopant diffusion/activation simulations. Atomistic potential profile for device simulation is calculated from discrete dopant atom positions by incorporating the long-range part of Coulomb potential. This simulation was used to investigate the variations in characteristics of sub-100 nm CMOS devices induced by realistic dopant fluctuations considering practical device fabrication processes. In particular, sensitivity analysis of the threshold voltage fluctuation was performed in terms of the independent dopant contribution, such as that of the dopant in the source/drain or channel region.

A new analysis method for random dopant induced threshold voltage fluctuations by using Monte Carlo ion implantation were presented. The method was applied to investigate V_t fluctuations due to statistical variation of pocket dopant profile in 0.1µm MOSFET's by 3D process-device simulation system. This method is very useful to analyze a statistical fluctuation in sub-100 nm MOSFET's efficiently.

For tracking electromigration induced evolution of voids a diffuse interface model is applied. We assume an interconnect as two-dimensional electrically conducting via which contains initially a circular void. The diffuse interface governing equation was solved applying a finite element scheme with a robust local grid adaptation algorithm. Simulations were carried out for voids exposed to high current. An influence of the void dynamics on the resistance of interconnect is investigated. In the case of the interconnect via it was shown that a migrating void exactly follows the current flow, retaining its stability, but due to change of shape and position causes significant fluctuations in interconnect resistance.

A software module for the three-dimensional simulation of etching processes has been developed. It works on multilayer structures given as triangulated surface meshes. The mesh is moved nodewise according to rates which, in this work, have been determined from isotropic and anisotropic components. An important feature of the algorithm is the automatic detection of triple lines along mask edges and the refinement of triangles at these triple lines. This allows for the simulation of underetching. The capabilities of the algorithm are demonstrated by several examples such as the simulation of glass etching for the fabrication of a phase shift mask for optical lithography and the etching of an STI trench structure. Moreover, etch profiles of a silicon substrate covered by an oxide mask are shown for different parameters of the etch components. Spacer etching has also been performed. Furthermore, a specific algorithm for the simulation of purely isotropic etching is described and demonstrated.

Recently, a new approach was presented to determine the high-frequency response of on-chip passives and interconnects. The method solves the electric scalar and magnetic vector potentials in a prescribed gauge. The latter one is included by introducing an additional independent scalar field, whose field equation needs to be solved. This additional field is a mathematical aid that allows for the construction of a gauge-conditioned, regular matrix representation of the curl-curl operator acting on edge elements. This paper reports on the convergence properties of the new method and shows the first results of this new calculation scheme for VLSI-based structures at high frequencies. The high-frequent behavior of the substrate current, the skin effect and current crowding is evaluated.

It is still an open problem to elucidate the scaling merits of an embedded SRAM with Low Operating Power (LOP) MOSFETs fabricated in 50, 70 and 100 nm CMOS technology nodes. Taking into account a realistic SRAM cell layout, we evaluated the parasitic capacitance of the bit line (BL) as well as the word line (WL) in each generation. By means of a 3-Dimensional (3D) interconnect simulator (Raphael), we focused on the scaling merit through a comparison of the simulated SRAM BL delay for each CMOS technology node. In this paper, we propose two kinds of original interconnect structure which modify ITRS (International Technology Roadmap for Semiconductors), and make it clear that the original interconnect structures with reduced gate overlap capacitance guarantee the scaling merits of SRAM cells fabricated with LOP MOSFETs in 50 and 70 nm CMOS technology nodes.

In this paper, we propose a TCAD driven hot carrier reduction methodology of 3.3 V I/O pMOSFETs design. The hot carrier reliability of surface channel I/O pMOSFET having drain structure in common with core devices has a critical issue. It is substantially important for the high-reliability devices to reduce both drain avalanche and channel hot hole components. The drain structures are successfully optimized in short time by applications of TCAD local models. Considering tradeoffs between hot carrier injection (HCI) and drive current (I_ON), SDE/HALO of both core and I/O transistors can be totally optimized for reduction of process-steps and/or photo-masks.

We propose an effective dopant pile-up model which is useful for device optimization in a short-term. Our purpose is that the model provides speedy calculation for numerous simulations constructed by design of experiment (DoE), and the calibration is also easy in practical range of process condition. The dopant pile-up in the Si/SiO₂ interface is calculated using a non-pair diffusion model that solves one equation for each impurity, considering an essential physics where RSCE is due to the dopant pile-up in the Si/SiO₂ interface. A non-pair diffusion for dopants and point defects is adequate for time length which can ignore their reactions. The key for the modeling of RSCE is that the dependence on various processes such as channel implantation and annealing conditions can be reproduced in the local process window. The capability of the model is investigated though the comparison to measurements in actual n-channel MOSFETs for different process technologies. We also check the prediction accuracy of the dopant profiles using our model. As a result, the optimization of 4 parameters for 25 jobs based on DoE is possible less than 2 hours using our model.

A high power dissipation density in today's miniature electronic/mechanical systems makes on-chip thermal management very important. In order to achieve quick to evaluate, yet accurate electro-thermal models, needed for the thermal management of microsystems, a model order reduction is necessary. In this paper, we present an automatic, Krylov-subspace-based order reduction of a electro-thermal model, which we illustrate by a novel type of micropropulsion device. Numerical simulation results of the full finite element model and the reduced order model, that describes the transient electro-thermal behavior, are presented. A comparison between Krylov-subspace-based order reduction, order reduction using control theoretical approaches and commercially available reduced order modeling has been performed. A Single-Input-Single-Output setup for the Arnoldi reduction algorithm was proved to be sufficient to accurately represent the complete time-dependent temperature distribution of the device.

In this paper, we investigate the electron-hole energy states and energy gap in three-dimensional (3D) InAs/GaAs quantum rings and dots with different shapes under external magnetic fields. Our realistic model formulation includes: (i) the effective mass Hamiltonian in non-parabolic approximation for electrons, (ii) the effective mass Hamiltonian in parabolic approximation for holes, (iii) the position- and energy-dependent quasi-particle effective mass approximation for electrons, (iv) the finite hard wall confinement potential, and (v) the Ben Daniel-Duke boundary conditions. To solve the 3D nonlinear problem without any fitting parameters, we have applied the nonlinear iterative method to obtain self-consistent solutions. Due to the penetration of applied magnetic fields into torus ring region, for ellipsoidal- and rectangular-shaped quantum rings we find nonperiodical oscillations of the energy gap between the lowest electron and hole states as a function of external magnetic fields. The nonperiodical oscillation is different from 1D periodical argument and strongly dependent on structure shape and size. The result is useful to study magneto-optical properties of the nanoscale quantum rings and dots.

Small-size MOSFETs are becoming core devices in RF applications because of improved high frequency characteristics. For reliable design of RF integrated circuits operating at the GHz range, accurate modeling of small-size MOSFET characteristics is indispensable. In MOSFETs with reduced gate length (L_g), the lateral field along the MOSFET channel is becoming more pronounced, causing short-channel effects. These effects should be included in the device modeling used for circuit simulation. In this work, we investigated the effects of the field gradient in the gate-drain capacitance (C_gd). 2-Dimensional (2D) simulations done with MEDICI show that the field gradient, as it influences the channel condition, induces a capacitance which is visible in the MOSFET saturation operation. Changes in C_gd is incorporated in the modeling by an induced capacitance approach. The new approach has been successfully implemented in the surface-potential based model HiSIM (Hiroshima-university STARC IGFET Model) and is capable of reproducing accurately the measured C_gd-L_g characteristics, which are particularly significant for pocket-implant technology. Results show that pocket-implantation introduces a steep potential increase near the drain region, which results to a shift of the C_gd transition region (from linear to saturation) to lower bias voltages. C_gd at saturation decreases with L_g due to steeper surface potential and increased impurity concentration effects at reduced L_g.

RF noise in quarter-micron nMOSFETs is analysed on the device level based on Shockley's impedance field method. The impact of different transport models and physical parameters is discussed in detail. Well-calibrated drift-diffusion and energy-balance models give very similar results for noise current spectral densities and noise figures. We show by numerical simulations with the general-purpose device simulator DESSIS__ISE that the hot-electron effect on RF noise is unimportant under normal operating conditions and that thermal substrate noise is dominant below 0.5 GHz. The contribution of energy-current fluctuations to the terminal noise is found to be negligible. Application of noise sources generated in bulk full-band Monte Carlo simulations changes the noise figures considerably, which underlines the importance of proper noise source models for far-from-equilibrium conditions.

We have developed a fiber physical contact (FPC) connector for the high-density connection of optical fibers. This connector individually aligns multiple bare fibers in micro-holes without ferrules and realizes physical contact by using the buckling force of the fibers themselves. The fiber endfaces must be tapered to allow the fibers to be inserted into the micro-holes. The endfaces must also be polished so that they realize physical contact (PC) with excellent optical performance. For each process, we examined the required shape and processing condition of the fiber endface for the FPC connector. As regards tapering, we determined the processing condition for achieving a target tapering angle and developed a non-breaking process with the optical fibers bent. In terms of polishing, we revealed that it is important for the fiber endface angle error to be less than 0.7 degrees if we are to achieve excellent optical performance. These results allowed us to fabricate an FPC connector that exhibited excellent levels of optical performance.

A dual-modulus (divide-by-128/129) prescaler has been designed based on 0.25-µm CMOS technology employing new D-flip-flops. The new D-flip-flops are free from glitch problems due to internal charge sharing. Transistor merging technique has been employed to reduce the number of transistors and to secure reliable high-speed operation. At the 2.5-V supply voltage, the prescaler using the proposed dynamic D-flip-flops can operate up to the frequency of 2.95-GHz, and consumes about 10% and about 27% less power than Yuan/Svensson's and Huang's circuits, respectively.

This work describes an 8b 200 MHz time-interleaved subranging analog-to-digital converter (ADC) based on a single-poly digital CMOS process. Two fine ADCs for lower digital bits of the proposed ADC employ a time-sharing double- channel architecture to increase the sampling speed and a new reference voltage switching scheme to reduce the settling time of the reference voltages and the chip area. The proposed intermeshed resistor string, which generates reference voltages for fine ADCs, improves the linearity and the settling time of the reference voltages simultaneously. The proposed sample-and-hold amplifier employs an input dynamic common mode feedback circuit for high dynamic performance, based on conventional common-drain amplifiers and passive differential circuits.