This paper proposes a buried-LATID structure featuring a peaked vertical profile around gate edge for the n- drain unlike the reported conventional LATID structure. As compared to the conventional LATID FETs, the deep-submicron buried-LATID FETs achieve improved circuit speed by 7% (50% compared to LDD FETs) due to suppressed gate-to-drain capacitance and improved lifetime by 10 times (300 times compared to LDD FETs). The buried-LATID FETs are very promising for deep-submicron MOSFETs to achieve improved performance and hot-carrier reliability at the same time.

In this paper, a three part algorithm is employed to obtain stable convergence during stress dependent oxidation simulation using the finite element method is presented. By introducing (1) a reduced integration formulation, (2) an averaging procedure for the mid-side node velocities at the Si/SiO2 interface, and (3) a three-node element to discretize the oxidant diffusion equation, major improvements in achieving stable convergence are realized during stress dependent oxidation simulation. This technique is generally applicable for an oxidation simulator using the finite element method.

A new analysis method for random dopant induced threshold voltage fluctuations by using Monte Carlo ion implantation were presented. The method was applied to investigate Vt fluctuations due to statistical variation of pocket dopant profile in 0.1µm MOSFET's by 3D process-device simulation system. This method is very useful to analyze a statistical fluctuation in sub-100 nm MOSFET's efficiently.