This work describes an 8b 200 MHz time-interleaved subranging analog-to-digital converter (ADC) based on a single-poly digital CMOS process. Two fine ADCs for lower digital bits of the proposed ADC employ a time-sharing double- channel architecture to increase the sampling speed and a new reference voltage switching scheme to reduce the settling time of the reference voltages and the chip area. The proposed intermeshed resistor string, which generates reference voltages for fine ADCs, improves the linearity and the settling time of the reference voltages simultaneously. The proposed sample-and-hold amplifier employs an input dynamic common mode feedback circuit for high dynamic performance, based on conventional common-drain amplifiers and passive differential circuits.

This paper describes an 8b 52 MHz CMOS subranging analog-to-digital converter (ADC) for digital subscriber loop applications. The proposed ADC based on an improved time-interleaved architecture removes the holding time which is typically observed in the conventional double-channel subranging ADC's to increase the throughput rate by 50%. The ADC employs the interpolation technique in the back-end subranging ADC's for residue signal processing to minimize the active die area and the power consumption. A layout technique is adopted to reduce the plasma-induced comparator offsets and the die area of the ADC. The fabricated and measured prototype ADC in a 0.8 µm CMOS process shows nonlinearities less than 0.4 LSB and the signal-to-noise-and-distortion ratio of 43 dB for a 1 MHz input at a 52 MHz sampling rate with 230 mW.