An 8b 52 MHz Double-Channel CMOS Subranging A/D Converter for DSL Applications

Sung-Ho LEE; Jung-Woong MOON; Seung-Hoon LEE

An 8b 52 MHz Double-Channel CMOS Subranging A/D Converter for DSL Applications

Sung-Ho LEE, Jung-Woong MOON, Seung-Hoon LEE

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This paper describes an 8b 52 MHz CMOS subranging analog-to-digital converter (ADC) for digital subscriber loop applications. The proposed ADC based on an improved time-interleaved architecture removes the holding time which is typically observed in the conventional double-channel subranging ADC's to increase the throughput rate by 50%. The ADC employs the interpolation technique in the back-end subranging ADC's for residue signal processing to minimize the active die area and the power consumption. A layout technique is adopted to reduce the plasma-induced comparator offsets and the die area of the ADC. The fabricated and measured prototype ADC in a 0.8 µm CMOS process shows nonlinearities less than 0.4 LSB and the signal-to-noise-and-distortion ratio of 43 dB for a 1 MHz input at a 52 MHz sampling rate with 230 mW.

Publication: IEICE TRANSACTIONS on Electronics Vol.E84-C No.4 pp.470-474

Publication Date: 2001/04/01

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Type of Manuscript: PAPER

Category: Integrated Electronics

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Sung-Ho LEE, Jung-Woong MOON, Seung-Hoon LEE, "An 8b 52 MHz Double-Channel CMOS Subranging A/D Converter for DSL Applications" in IEICE TRANSACTIONS on Electronics, vol. E84-C, no. 4, pp. 470-474, April 2001, doi: .
Abstract: This paper describes an 8b 52 MHz CMOS subranging analog-to-digital converter (ADC) for digital subscriber loop applications. The proposed ADC based on an improved time-interleaved architecture removes the holding time which is typically observed in the conventional double-channel subranging ADC's to increase the throughput rate by 50%. The ADC employs the interpolation technique in the back-end subranging ADC's for residue signal processing to minimize the active die area and the power consumption. A layout technique is adopted to reduce the plasma-induced comparator offsets and the die area of the ADC. The fabricated and measured prototype ADC in a 0.8 µm CMOS process shows nonlinearities less than 0.4 LSB and the signal-to-noise-and-distortion ratio of 43 dB for a 1 MHz input at a 52 MHz sampling rate with 230 mW.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e84-c_4_470/_p

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@ARTICLE{e84-c_4_470,
author={Sung-Ho LEE, Jung-Woong MOON, Seung-Hoon LEE, },
journal={IEICE TRANSACTIONS on Electronics},
title={An 8b 52 MHz Double-Channel CMOS Subranging A/D Converter for DSL Applications},
year={2001},
volume={E84-C},
number={4},
pages={470-474},
abstract={This paper describes an 8b 52 MHz CMOS subranging analog-to-digital converter (ADC) for digital subscriber loop applications. The proposed ADC based on an improved time-interleaved architecture removes the holding time which is typically observed in the conventional double-channel subranging ADC's to increase the throughput rate by 50%. The ADC employs the interpolation technique in the back-end subranging ADC's for residue signal processing to minimize the active die area and the power consumption. A layout technique is adopted to reduce the plasma-induced comparator offsets and the die area of the ADC. The fabricated and measured prototype ADC in a 0.8 µm CMOS process shows nonlinearities less than 0.4 LSB and the signal-to-noise-and-distortion ratio of 43 dB for a 1 MHz input at a 52 MHz sampling rate with 230 mW.},
keywords={},
doi={},
ISSN={},
month={April},}

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TY - JOUR
TI - An 8b 52 MHz Double-Channel CMOS Subranging A/D Converter for DSL Applications
T2 - IEICE TRANSACTIONS on Electronics
SP - 470
EP - 474
AU - Sung-Ho LEE
AU - Jung-Woong MOON
AU - Seung-Hoon LEE
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E84-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2001
AB - This paper describes an 8b 52 MHz CMOS subranging analog-to-digital converter (ADC) for digital subscriber loop applications. The proposed ADC based on an improved time-interleaved architecture removes the holding time which is typically observed in the conventional double-channel subranging ADC's to increase the throughput rate by 50%. The ADC employs the interpolation technique in the back-end subranging ADC's for residue signal processing to minimize the active die area and the power consumption. A layout technique is adopted to reduce the plasma-induced comparator offsets and the die area of the ADC. The fabricated and measured prototype ADC in a 0.8 µm CMOS process shows nonlinearities less than 0.4 LSB and the signal-to-noise-and-distortion ratio of 43 dB for a 1 MHz input at a 52 MHz sampling rate with 230 mW.
ER -