This paper describes an 8b 52 MHz CMOS subranging analog-to-digital converter (ADC) for digital subscriber loop applications. The proposed ADC based on an improved time-interleaved architecture removes the holding time which is typically observed in the conventional double-channel subranging ADC's to increase the throughput rate by 50%. The ADC employs the interpolation technique in the back-end subranging ADC's for residue signal processing to minimize the active die area and the power consumption. A layout technique is adopted to reduce the plasma-induced comparator offsets and the die area of the ADC. The fabricated and measured prototype ADC in a 0.8 µm CMOS process shows nonlinearities less than 0.4 LSB and the signal-to-noise-and-distortion ratio of 43 dB for a 1 MHz input at a 52 MHz sampling rate with 230 mW.

An 8-to 10-bit CMOS A/D converter with a conversion rate of more than 16 megasample/second is required in consumer video systems. Subranging architecture is widely used to realize such A/D converters. This architecture, however, exhibits an reference voltage error caused by resistor ladder loadings. The error has been discussed with respect to a flash A/D converter by Dingwall. However, it can not be applied for a subranging A/D converter as it is. The analysis of this error is very important in realizing the desired accuracy of a subranging A/D converter. This paper describes a static analysis to improve the linearity, and reports the results of this analysis for two typical types, one with invividual comparator arrays for coarse and fine A/D conversions, and the other with the same comparator array for both conversions. This analysis makes it clear that a subranging A/D converter has unique saw-tooth characteristic in fine linearity errors. Furthermore, this analysis clarifies what conditions are necessary to achieve the desired accuracy. It is necessary, for example, that the product of the total input capacitance of the comparators C, the conversion rate fs and the total ladder resistance R is less than 0.03 in A/D converters with individual comparator arrays and 0.016 in A/D converters with the same comparator array in order to achieve 10-bit accuracy.