Static Linearity Error Analysis of Subranging A/D Converters

Takashi OKUDA; Toshio KUMAMOTO; Masao ITO; Takahiro MIKI; Keisuke OKADA; Tadashi SUMI

Static Linearity Error Analysis of Subranging A/D Converters

Takashi OKUDA, Toshio KUMAMOTO, Masao ITO, Takahiro MIKI, Keisuke OKADA, Tadashi SUMI

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An 8-to 10-bit CMOS A/D converter with a conversion rate of more than 16 megasample/second is required in consumer video systems. Subranging architecture is widely used to realize such A/D converters. This architecture, however, exhibits an reference voltage error caused by resistor ladder loadings. The error has been discussed with respect to a flash A/D converter by Dingwall. However, it can not be applied for a subranging A/D converter as it is. The analysis of this error is very important in realizing the desired accuracy of a subranging A/D converter. This paper describes a static analysis to improve the linearity, and reports the results of this analysis for two typical types, one with invividual comparator arrays for coarse and fine A/D conversions, and the other with the same comparator array for both conversions. This analysis makes it clear that a subranging A/D converter has unique saw-tooth characteristic in fine linearity errors. Furthermore, this analysis clarifies what conditions are necessary to achieve the desired accuracy. It is necessary, for example, that the product of the total input capacitance of the comparators C, the conversion rate f_s and the total ladder resistance R is less than 0.03 in A/D converters with individual comparator arrays and 0.016 in A/D converters with the same comparator array in order to achieve 10-bit accuracy.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E79-A No.2 pp.210-216

Publication Date: 1996/02/25

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Type of Manuscript: Special Section PAPER (Special Section on Analog Technologies in Submicron Era)

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Takashi OKUDA, Toshio KUMAMOTO, Masao ITO, Takahiro MIKI, Keisuke OKADA, Tadashi SUMI, "Static Linearity Error Analysis of Subranging A/D Converters" in IEICE TRANSACTIONS on Fundamentals, vol. E79-A, no. 2, pp. 210-216, February 1996, doi: .
Abstract: An 8-to 10-bit CMOS A/D converter with a conversion rate of more than 16 megasample/second is required in consumer video systems. Subranging architecture is widely used to realize such A/D converters. This architecture, however, exhibits an reference voltage error caused by resistor ladder loadings. The error has been discussed with respect to a flash A/D converter by Dingwall. However, it can not be applied for a subranging A/D converter as it is. The analysis of this error is very important in realizing the desired accuracy of a subranging A/D converter. This paper describes a static analysis to improve the linearity, and reports the results of this analysis for two typical types, one with invividual comparator arrays for coarse and fine A/D conversions, and the other with the same comparator array for both conversions. This analysis makes it clear that a subranging A/D converter has unique saw-tooth characteristic in fine linearity errors. Furthermore, this analysis clarifies what conditions are necessary to achieve the desired accuracy. It is necessary, for example, that the product of the total input capacitance of the comparators C, the conversion rate f_s and the total ladder resistance R is less than 0.03 in A/D converters with individual comparator arrays and 0.016 in A/D converters with the same comparator array in order to achieve 10-bit accuracy.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e79-a_2_210/_p

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@ARTICLE{e79-a_2_210,
author={Takashi OKUDA, Toshio KUMAMOTO, Masao ITO, Takahiro MIKI, Keisuke OKADA, Tadashi SUMI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Static Linearity Error Analysis of Subranging A/D Converters},
year={1996},
volume={E79-A},
number={2},
pages={210-216},
abstract={An 8-to 10-bit CMOS A/D converter with a conversion rate of more than 16 megasample/second is required in consumer video systems. Subranging architecture is widely used to realize such A/D converters. This architecture, however, exhibits an reference voltage error caused by resistor ladder loadings. The error has been discussed with respect to a flash A/D converter by Dingwall. However, it can not be applied for a subranging A/D converter as it is. The analysis of this error is very important in realizing the desired accuracy of a subranging A/D converter. This paper describes a static analysis to improve the linearity, and reports the results of this analysis for two typical types, one with invividual comparator arrays for coarse and fine A/D conversions, and the other with the same comparator array for both conversions. This analysis makes it clear that a subranging A/D converter has unique saw-tooth characteristic in fine linearity errors. Furthermore, this analysis clarifies what conditions are necessary to achieve the desired accuracy. It is necessary, for example, that the product of the total input capacitance of the comparators C, the conversion rate f_s and the total ladder resistance R is less than 0.03 in A/D converters with individual comparator arrays and 0.016 in A/D converters with the same comparator array in order to achieve 10-bit accuracy.},
keywords={},
doi={},
ISSN={},
month={February},}

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TY - JOUR
TI - Static Linearity Error Analysis of Subranging A/D Converters
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 210
EP - 216
AU - Takashi OKUDA
AU - Toshio KUMAMOTO
AU - Masao ITO
AU - Takahiro MIKI
AU - Keisuke OKADA
AU - Tadashi SUMI
PY - 1996
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E79-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 1996
AB - An 8-to 10-bit CMOS A/D converter with a conversion rate of more than 16 megasample/second is required in consumer video systems. Subranging architecture is widely used to realize such A/D converters. This architecture, however, exhibits an reference voltage error caused by resistor ladder loadings. The error has been discussed with respect to a flash A/D converter by Dingwall. However, it can not be applied for a subranging A/D converter as it is. The analysis of this error is very important in realizing the desired accuracy of a subranging A/D converter. This paper describes a static analysis to improve the linearity, and reports the results of this analysis for two typical types, one with invividual comparator arrays for coarse and fine A/D conversions, and the other with the same comparator array for both conversions. This analysis makes it clear that a subranging A/D converter has unique saw-tooth characteristic in fine linearity errors. Furthermore, this analysis clarifies what conditions are necessary to achieve the desired accuracy. It is necessary, for example, that the product of the total input capacitance of the comparators C, the conversion rate f_s and the total ladder resistance R is less than 0.03 in A/D converters with individual comparator arrays and 0.016 in A/D converters with the same comparator array in order to achieve 10-bit accuracy.
ER -