An 8-to 10-bit CMOS A/D converter with a conversion rate of more than 16 megasample/second is required in consumer video systems. Subranging architecture is widely used to realize such A/D converters. This architecture, however, exhibits an reference voltage error caused by resistor ladder loadings. The error has been discussed with respect to a flash A/D converter by Dingwall. However, it can not be applied for a subranging A/D converter as it is. The analysis of this error is very important in realizing the desired accuracy of a subranging A/D converter. This paper describes a static analysis to improve the linearity, and reports the results of this analysis for two typical types, one with invividual comparator arrays for coarse and fine A/D conversions, and the other with the same comparator array for both conversions. This analysis makes it clear that a subranging A/D converter has unique saw-tooth characteristic in fine linearity errors. Furthermore, this analysis clarifies what conditions are necessary to achieve the desired accuracy. It is necessary, for example, that the product of the total input capacitance of the comparators C, the conversion rate fs and the total ladder resistance R is less than 0.03 in A/D converters with individual comparator arrays and 0.016 in A/D converters with the same comparator array in order to achieve 10-bit accuracy.

In ISDN and ATM, performance evaluation of packetized voice is an important problem. To analyse the superposed voice packets from a number of voice sources, the Markov modulated Poisson process (MMPP) has been used for approximating the superposed non-renewal process. In this approximation, a large computer time was needed for determining the MMPP parameters by the numerical inversion of Laplace transform. In this paper, introducing the index of skewness for counts as well as the index of dispersion, and using their conservation low, limiting property and differential coefficient at the origin, we propose a simplified method for determining the parameters.

WLANs have become increasingly popular and widely deployed. The MAC protocol is one of the important technology of the WLAN and affects communication efficiency directly. In this paper, focusing on MAC protocol, we propose a novel protocol that network nodes dynamically optimize their backoff process to achieve high throughput while supporting satisfied QoS. A distributed MAC protocol has an advantage that no infrastructure such as access point is necessary. On the other hand, total throughput decreases heavily and cannot guarantee QoS under high traffic load, which needs to be improved. Through theoretical analysis, we find that the average idle interval can represent current network traffic load and can be used together with estimated number of nodes for setting optimal CW. Since necessary indexes can be obtained directly through observing channel, our scheme based on those indexes will not increase any added load to networks, which makes our schemes simpler and more effective. Through simulation comparison with conventional method, we show that our scheme can greatly enhance the throughput and the QoS no matter the network is in saturated or non-saturated case, while maintaining good fairness.

This paper describes the 10-bit 50 MS/s pipelined CMOS A/D Converter using a "reference feed-forward architecture." In this architecture, reference voltage generated in a reference generator block and residual voltage from a DA/subtractor block are fed to the next stage. The reference generator block and DA/subtractor block are constructed using resistive-load, low-gain differential amplifiers. The high-gain, high-speed amplifiers consuming much power are not used. Therefore, the power consumption of this ADC is reduced. The gain matching of the reference voltage with the internal signal range is achieved through the introduction of the reference generator block having the same characteristics as a DA/subtractor block. Each offset voltage of the differential amplifier in the reference generator block and the DA/subtractor block is canceled by the offset cancellation technique, individually. In addition, the front-end sample/hold circuit is eliminated to reduce power consumption. Because of the introduction of high-speed comparators based on the source follower and latch circuit into the first stage A/D subconverter, analog bandwidth is not degraded. This ADC has been fabricated in double-polysilicon, double-metal, 0.5µm CMOS technology, and it operates at 50 MS/s with a 300-mW (Vdd=3.0 V) power consumption. The differential linearity error of less than +/-1 LSB is obtained.

Unlike Wi-Fi, Broadband Wireless Access (BWA) technology provides a high-speed communication in a wide area. The IEEE 802.16 (WiMAX) standard of wireless mesh networks is one of the widely used BWA standards. WiMAX mesh mode achieves data transmission in conflict-free manner in multihop networks by using the control messages (three way handshake messages or MSH-DSCH messages) to reserve channel for sending data. Concurrently, the coordination of three way handshake messages depends on the mechanism named Election based Transmission Timing (EBTT). However, IEEE 802.16 mesh mode uses a static holdoff algorithm, which leads to a low performance in the majority of cases. In this paper, after analyzing the IEEE 802.16 mesh mode with coordinated distributed scheduling, we propose a novel method to improve the throughput by a dynamic holdoff algorithm. The simulation results show that our proposal gets a better throughput performance.

An Ad Hoc network is a collection of wireless mobile nodes dynamically forming a temporary network without the use of any existing network infrastructure or centralized administration. The choice of medium access is difficult in Ad Hoc networks due to the time-varying network topology and the lack of centralized control. In this paper, we propose a novel multichannel schedule-based Medium Access Control (MAC) protocol for Ad Hoc networks named Multichannel Reservation Protocol for TDMA-based networks (MRPT). MRPT ensures collision free in successfully reserved data links, even when hidden terminals exist. The reservation of MRPT is based a control channel and in order to improve throughput we propose Four-Phase-Two-Division (FPTD) as a media access scheme of the control channel for broadcasting control or reservation messages. In FPTD, the collision can be solved rapidly with an efficient backoff algorithm which results in that system block is avoided in case of high traffic. In this paper, we also present the throughput performance of MRPT, which shows a high value and no system block even in case of high traffic load.