A 10b 100 MS/s 1.4 mm2 56 mW 0.18 µm CMOS A/D Converter with 3-D Fully Symmetrical Capacitors
Summary :
This work proposes a 10b 100 MS/s 1.4 mm2 CMOS ADC for low-power multimedia applications. The proposed two-step pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The wide-band SHA employs a gate-bootstrapping circuit to handle both single-ended and differential inputs of 1.2 Vp-p at 10b accuracy while the second-stage flash ADC employs open-loop offset sampling techniques to achieve 6b resolution. A 3-D fully symmetrical layout reduces the capacitor and device mismatch of the first-stage MDAC. The low-noise references are integrated on chip with optional off-chip voltage references. The prototype 10b ADC implemented in a 0.18 µm CMOS shows the maximum measured DNL and INL of 0.59LSB and 0.77LSB, respectively. The ADC demonstrates an SNDR of 53.7 dB, an SFDR of 61.5 dB, and the power dissipation of 56 mW at 100 MS/s.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E89-C No.5 pp.630-635
- Publication Date
- 2006/05/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1093/ietele/e89-c.5.630
- Type of Manuscript
- PAPER
- Category
- Electronic Circuits
Authors
Keyword
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Byoung-Han MIN, Young-Jae CHO, Hee-Sung CHAE, Hee-Won PARK, Seung-Hoon LEE, "A 10b 100 MS/s 1.4 mm2 56 mW 0.18 µm CMOS A/D Converter with 3-D Fully Symmetrical Capacitors" in IEICE TRANSACTIONS on Electronics,
vol. E89-C, no. 5, pp. 630-635, May 2006, doi: 10.1093/ietele/e89-c.5.630.
Abstract: This work proposes a 10b 100 MS/s 1.4 mm2 CMOS ADC for low-power multimedia applications. The proposed two-step pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The wide-band SHA employs a gate-bootstrapping circuit to handle both single-ended and differential inputs of 1.2 Vp-p at 10b accuracy while the second-stage flash ADC employs open-loop offset sampling techniques to achieve 6b resolution. A 3-D fully symmetrical layout reduces the capacitor and device mismatch of the first-stage MDAC. The low-noise references are integrated on chip with optional off-chip voltage references. The prototype 10b ADC implemented in a 0.18 µm CMOS shows the maximum measured DNL and INL of 0.59LSB and 0.77LSB, respectively. The ADC demonstrates an SNDR of 53.7 dB, an SFDR of 61.5 dB, and the power dissipation of 56 mW at 100 MS/s.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e89-c.5.630/_p
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@ARTICLE{e89-c_5_630,
author={Byoung-Han MIN, Young-Jae CHO, Hee-Sung CHAE, Hee-Won PARK, Seung-Hoon LEE, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 10b 100 MS/s 1.4 mm2 56 mW 0.18 µm CMOS A/D Converter with 3-D Fully Symmetrical Capacitors},
year={2006},
volume={E89-C},
number={5},
pages={630-635},
abstract={This work proposes a 10b 100 MS/s 1.4 mm2 CMOS ADC for low-power multimedia applications. The proposed two-step pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The wide-band SHA employs a gate-bootstrapping circuit to handle both single-ended and differential inputs of 1.2 Vp-p at 10b accuracy while the second-stage flash ADC employs open-loop offset sampling techniques to achieve 6b resolution. A 3-D fully symmetrical layout reduces the capacitor and device mismatch of the first-stage MDAC. The low-noise references are integrated on chip with optional off-chip voltage references. The prototype 10b ADC implemented in a 0.18 µm CMOS shows the maximum measured DNL and INL of 0.59LSB and 0.77LSB, respectively. The ADC demonstrates an SNDR of 53.7 dB, an SFDR of 61.5 dB, and the power dissipation of 56 mW at 100 MS/s.},
keywords={},
doi={10.1093/ietele/e89-c.5.630},
ISSN={1745-1353},
month={May},}
Copy
TY - JOUR
TI - A 10b 100 MS/s 1.4 mm2 56 mW 0.18 µm CMOS A/D Converter with 3-D Fully Symmetrical Capacitors
T2 - IEICE TRANSACTIONS on Electronics
SP - 630
EP - 635
AU - Byoung-Han MIN
AU - Young-Jae CHO
AU - Hee-Sung CHAE
AU - Hee-Won PARK
AU - Seung-Hoon LEE
PY - 2006
DO - 10.1093/ietele/e89-c.5.630
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E89-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 2006
AB - This work proposes a 10b 100 MS/s 1.4 mm2 CMOS ADC for low-power multimedia applications. The proposed two-step pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The wide-band SHA employs a gate-bootstrapping circuit to handle both single-ended and differential inputs of 1.2 Vp-p at 10b accuracy while the second-stage flash ADC employs open-loop offset sampling techniques to achieve 6b resolution. A 3-D fully symmetrical layout reduces the capacitor and device mismatch of the first-stage MDAC. The low-noise references are integrated on chip with optional off-chip voltage references. The prototype 10b ADC implemented in a 0.18 µm CMOS shows the maximum measured DNL and INL of 0.59LSB and 0.77LSB, respectively. The ADC demonstrates an SNDR of 53.7 dB, an SFDR of 61.5 dB, and the power dissipation of 56 mW at 100 MS/s.
ER -
English
