A 2-bit operational metal/silicon-oxide-nitride-oxide-silicon (MONOS/SONOS) nonvolatile memory using an asymmetric double-gate (ASDG) MOSFET was studied to double flash memory density. The 2-bit programming and erasing was performed by Fowler-Nordheim (FN) tunneling in a NAND array architecture using individually controlled gates. A threshold voltage shift of programmed states for the 2-bit operation was investigated with the aid of a SILVACO^® simulator in both sides of the gate by changing gate workfunctions and tunneling oxide thicknesses. In this paper, the scalability of the device down to 30 nm was demonstrated by numerical simulation. Additionally, guidelines of the 2-bit ASDG nonvolatile memory (NVM) structure and operational conditions were proposed for "program," "read," and "erase."

We present our recent results of the 10-bit data driver LSI for 42-inch diagonal TFT-LCD TV with full HD format. To develop data driver LSIs for a true 10-bit TFT-LCD TV with full HD (19201080) format, small chip area, low power consumption, and output uniformity between channels are key problems that must be solved. By applying a two-stage DAC which combines 8-bit resistor-string DAC and 2-bit binary weighted capacitor DAC, the area increase is limited to only 30% compared to the area of 8-bit resistor-string DAC. The output deviation between channels is successfully limited within 5 mV and the driver LSI with 414 outputs consumes the maximum total current of 16 mA when driving 42-inch HDTV panel. We confirmed that the picture with 10-bit shades of gray is much more natural than that with 8-bit shades of gray.

A new cell structure Power MOSFET, which exhibits a lower on-state resistance and lower gate charge than the conventional layout geometry, is proposed in this research. Vertical Power MOSFETs are generally designed by either squared (closed) cell or stripe (linear) cell geometry; each has its own advantages and drawbacks. Typically, closed cell design has lower on resistance but higher gate charge characteristics than the linear one. In this study, we propose, fabricate, and analyze a "wing cell" structure Power MOSFET, which can have lower on resistance and lower gate charge performances than the closed cell structure. In addition, the wing cell design can avoid the "closed concept" patents.

HfO_xN_y thin films formed by the electron cyclotron resonance (ECR) Ar/N₂ plasma nitridation of HfO₂ films were investigated for high-k gate insulator applications. HfO_xN_y thin films formed by the ECR Ar/N₂ plasma nitridation (60 s) of 1.5-nm-thick HfO₂ films, which were deposited on chemically oxidized Si(100) substrates, were found to be effective for suppressing interfacial layer growth or crystallization during postdeposition annealing (PDA) in N₂ ambient. After 900 PDA of for 5 min in N₂ ambient, it was found that HfSiON film with a relatively high dielectric constant was formed on the HfO_xN_y/Si interface by Si diffusion. An equivalent oxide thickness (EOT) of 2.0 nm and a leakage current density of 1.010^-3 A/cm² (at V_FB-1 V) were obtained. The effective mobility of the fabricated p-channel metal-insulator-semiconductor field-effect transistor (MISFET) with the HfO_xN_y gate insulator was 50 cm²/Vs, and the gate leakage current of the MISFET with the HfO_xN_y gate insulator was found to be well suppressed compared with the MISFET with the HfO₂ gate insulator after 900 PDA because of the nitridation of HfO₂.

For the measurement of the 3D surface of micro-solderballs in IC (Integrated Circuit) manufacturing inspection, a binary grating project lenses of high MTF (Modulation Transfer Function) with tilted project plane is designed in this paper. Using a combination of lenses and a tilted optical layout both on object and image plane, the wave-front aberrations are reduced and the nonlinear image distortion is corrected with nonlinearity compensation, This optical lens allows us to project the structured light pattern to the inspected objects efficiently for clear deformed coded imaging, it could be used to online measure 3D shape of micro-solderballs with high precision and accuracy.

Highly reliable GaN high electron mobility transistors (HEMTs) are demonstrated for 3G-wireless base station applications. A state-of-the-art 250-W AlGaN/GaN-HEMTs push-pull transmitter amplifier operated at a drain bias voltage of 50 V is addressed with high efficiency under W-CDMA signals. The amplifier, combined with a digital pre-distortion (DPD) system, also achieved an adjacent channel leakage power ratio (ACLR) of less than -50 dBc for 4-carrier W-CDMA signals. Memory effect and temperature characteristics are also discussed. A stable operation including gate leakage current under RF stress testing for 1000 h is demonstrated at a drain bias voltage of 60 V. AlGaN/GaN HEMTs on an n-type doped 3-inch SiC substrate is introduced towards low cost manufacturing for the first time.

To perform a comparative study, we experimented on two differential epitaxial structures, the conventional metamorphic high-electron-mobility-transistor (MHEMT) using the InAlAs/InGaAs/InAlAs structure and the InP-composite-channel MHEMT adopting the InAlAs/InGaAs/InP structure. Compared with the conventional MHEMT, the InP-composite-channel MHEMT shows improved breakdown performance; more than approximately 3.8 V. This increased breakdown voltage can be explained by the lower impact ionization coefficient of the InP-composite-channel MHEMT than that of the conventional MHEMT. The InP-composite-channel MHEMT also shows improved Radio Frequency characteristics of S₂₁ gain of approximately 4.35 dB at 50 GHz, and a cutoff frequency (f_T) and a maximum frequency of oscillation (f_max) of approximately 124 GHz and 240 GHz, respectively, were obtained. These are due to decreases in g_o and g_m.

This paper presents a design method of multi-stage, multi-way microstrip power dividers with the aim of constructing a compact low-loss power divider with numbers of outputs. First, an integration design technique of power dividers composed of multi-step, multi-furcation and mitered bends is described. Since the analytical technique is founded on the planar circuit approach combined with the segmentation method, the optimization of the circuit patterns can be performed in a reasonable short computation time. Next, the present method is applied to the design of broadband Nⁿ-way power dividers such as 3²-way power divider consisting of 3-way dividers in two-stage structures, respectively. In addition, a 12-way power divider constructed from a series connection of a 3-way and three 4-way dividers is designed. The dividers equivalently contain a 3-section Chebyshev transformer to realize broadband properties. As a result, the fractional bandwidths of nearly 85% and 66.7% for the power-split imbalance less than 0.2 dB and the return loss better than -20 dB are obtained for the 9- and 12-way power dividers, respectively. The validity of these design results is confirmed by a commercial em-simulator (Ansoft HFSS) and experiments.

This work proposes a 10b 100 MS/s 1.4 mm² CMOS ADC for low-power multimedia applications. The proposed two-step pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The wide-band SHA employs a gate-bootstrapping circuit to handle both single-ended and differential inputs of 1.2 Vp-p at 10b accuracy while the second-stage flash ADC employs open-loop offset sampling techniques to achieve 6b resolution. A 3-D fully symmetrical layout reduces the capacitor and device mismatch of the first-stage MDAC. The low-noise references are integrated on chip with optional off-chip voltage references. The prototype 10b ADC implemented in a 0.18 µm CMOS shows the maximum measured DNL and INL of 0.59LSB and 0.77LSB, respectively. The ADC demonstrates an SNDR of 53.7 dB, an SFDR of 61.5 dB, and the power dissipation of 56 mW at 100 MS/s.

This work describes an 8b 240 MS/s CMOS ADC as one of embedded core circuits for high-performance displays based on low-noise on-chip references and dual-mode inputs with the requirements of limited pins, low power, and small size at high speed. The proposed ADC uses externally connected pins only for analog inputs, digital outputs, and supplies. The ADC employs (1) a two-step pipeline architecture to optimize power and chip size at the target sampling frequency of 240 MHz, (2) advanced bootstrapping techniques to achieve high signal bandwidth in the input SHA, and (3) RC filter-based on-chip current and voltage references to improve noise performance with a power-off function for portable applications. The prototype ADC is implemented in a 0.18 µm CMOS and simultaneously integrated in a DVD system with dual-mode inputs. The prototype ADC shows the measured DNL and INL within 0.49LSB and 0.69LSB, and the SNDR and SFDR exceeding 38 dB and 50 dB for inputs up to the Nyquist frequency at 240 MS/s. The ADC consumes 104 mW at 240 MS/s and an active die area is 1.36 mm² .

This paper deals with the diffraction of TM plane wave by a perfectly conductive periodic surface. Applying the Rayleigh hypothesis, a linear equation system determining the diffraction amplitudes is derived. The linear equation is formally solved by Cramer's formula. It is then found that, when the angle of incidence becomes a low grazing limit, the amplitude of the specular reflection becomes -1 and any other diffraction amplitudes vanish for any perfectly conductive periodic surfaces with small roughness and gentle slope.

The perfect matched layer (PML) is formulated for the use in the constrained interpolation profile (CIP) method. Numerical results are presented to examine the performance of the proposed formulation of the PML in the case of two-dimensional TM wave. The results show that the proposed methods suppress the reflection effectively in comparison with the natural absorbing boundary condition of the CIP method. We have two methods to formulate the PML, and it is shown that the both methods have equal characteristics.

In this paper, we describe a bootstrapped nMOS switch that is modified to reduce leakage current for nMOS reversible energy recovery logic (nRERL) [1]. Conventional bootstrapped switches are not suitable for nRERL because they have nonadiabatic loss due to leakage current that flows while boosted. Therefore, we lowered the gate voltage of the isolation transistor in each bootstrapped switch to reduce this leakage current. With detailed analysis and simulation, we determined the range of the bias voltage, in which the switches can transfer full-swing input signals. We implemented a simple 8-bit nRERL microprocessor into silicon and measured its energy consumption to confirm our analysis. For the supply voltage of 1.8 V and the operating frequency of 880 kHz, we found that the microprocessor consumed about 8.5 pJ/cycle for 1.3 V < V_bias <1.6 V, which was just about a half of its energy consumption when V_bias = 1.7 V.

This paper presents a synthesizable testbench architecture based on a defined instruction for standalone mode verification. A set of instructions describes transitions of a signal. The set of instructions can be changed easily to describe different signal transitions by loading the different set of instructions on emulator's memory. The proposed testbench enables a fast emulation and increases flexibility and reusability by using an instruction set. To prove the performance of instruction based synthesizable testbench, we verified Bluetooth and IEEE 802.11a PHY baseband systems and compared their performance with those of co-sim mode and modified co-sim mode emulation.