In this paper, we design and implement a multi-protocol 13.56 MHz reader in software. In order to satisfy the timing constraint, three level optimizations called compile level, syntax level, and architectural level optimizations are applied. The execution time of optimized code is reduced by 85%, so that it satisfies timing requirement of a 60 MHz speed EISC processor. In addition, the binary code size is minimized to 211 KBytes which can be loaded on a 256 KB size memory.

A tight bound on the bit error probability for turbo codes is derived by refining the Sphere bound by means of the reduced value of the coefficients which apply Verdu theorem. This approach is simpler than other upper bound techniques and extends the reliable region of Eb/N0 for which the bound yields meaningful results.

For multilevel-coded modulation, the cut-off rate of multiple antenna systems over frequency-flat, fast fading channels is derived. Following Wozencraft's approach, a closed-form expression for the cut-off rate is obtained as a function of energy ratio per dimension It is shown that the maximum value of cut-off rate increases linearly with the number of transmit antennas.

This paper presents a calibration scheme for delay mismatch between envelope and phase in the OFDM polar transmitter. An asynchronous delay detection method is proposed to avoid using a complicated signal processing algorithm or synchronous elements which need high clocking rates for detecting small delay mismatch. This scheme uses buffer delay chains to estimate the mismatch and then the estimated delay values are asynchronously stored in registers. It is verified that the proposed scheme well suites application to the OFDM polar transmitter through SPW, Matlab and HDL simulations. It achieves the margin of about 20 dB at 20 MHz offset, 10 dB at 40 MHz offset in terms of spectral limit specified in WLAN standard.

In the paper, we introduce TLM methodology focusing on IEEE 802.11 WLAN as a derivative system. Decomposing the entire system into several computation components, we analyzed the property of each transaction, resulting in the TLM. In the case of shared bus, the simulation results show the effect of communication architecture such as bus protocol and bus parameters on the system performance.

A multiphase low-jitter delay-locked loop (DLL) with harmonic-lock prevention, targeted at a gigabit parallel link interface, is delineated. A three-input four-state dynamic phase detector (PD) is proposed to obviate harmonic locking. Employing a low-jitter delay element and a new type of PD, the DLL is compact and feasible in its nature. The DLL is designed using a 0.35 µm 2P4M CMOS process with 3.3 V supply. Experimental results show that the circuit avoids false locking.

The depth-first sphere decoder (SD) and the K-best algorithm have been widely studied as near optimum detectors. Depth-first SD has a non-deterministic computational throughput and K-best requires a sorting unit whose complexity is significant when a large K is used together with high modulation constellations. In this letter, we propose a MIMO detector that employs the trellis structure instead of the conventional tree searching. This detector can keep the computational throughput constant and reduce the complexity because the sorting is not required. From the simulation and complexity analysis, we investigate the advantage and drawback of the proposed detector.

This paper presents a synthesizable testbench architecture based on a defined instruction for standalone mode verification. A set of instructions describes transitions of a signal. The set of instructions can be changed easily to describe different signal transitions by loading the different set of instructions on emulator's memory. The proposed testbench enables a fast emulation and increases flexibility and reusability by using an instruction set. To prove the performance of instruction based synthesizable testbench, we verified Bluetooth and IEEE 802.11a PHY baseband systems and compared their performance with those of co-sim mode and modified co-sim mode emulation.

This paper presents a fast and systematic architecture exploration method that realizes an efficient IEEE 802.11e based hardware/software co-design Medium Access Control (MAC) system architecture, which can achieve near theoretical MAC throughput for burst data transmission while complying with strict channel access time requirements. Our design approach uses SystemC based Transaction Level Modeling (TLM) framework to integrate reconfigurable general purpose computing and communication resources into the application model for rapid evaluation of core parameters, system performance, and application specific optimizations. As a result, a MAC system architecture that achieves a simulated MAC throughput of more than 100 Mbps when transmitted at 260 Mbps of Physical Layer (PHY) data rate is obtained. This result is verified with X-X-IMPLEMENTATION on a Xilinx Field-Programmable Gate Array (FPGA) board.

With the growing demand for high-performance multimedia applications over wireless channels, we need to develop a Medium Access Control (MAC) system that supports high throughput and quality of service enhancements. This paper presents the standard analysis, design architecture and design issues leading to the implementation of an IEEE 802.11e based MAC system that supports MAC throughput of over 100 Mbps. In order to meet the MAC layer timing constraints, a hardware/software co-design approach is adopted. The proposed MAC architecture is implemented on the Xilinx Virtex-II Pro Field-Programmable Gate Array (FPGA) (XC2VP70-5FF1704C) prototype, and connected to a host computer through an external Universal Serial Bus (USB) interface. The total FPGA resource utilization is 11,508 out of 33,088 (34%) available slices. The measured MAC throughput is 100.7 Mbps and 109.2 Mbps for voice and video access categories, transmitted at a data rate of 260 Mbps based on IEEE 802.11n Physical Layer (PHY), using the contention-based hybrid coordination function channel access mechanism.

In this paper, a Turbo codec with reduced number of iterations is proposed. By inserting an even parity-check bit every six information bit, the coder can increase the minimum distance of the codewords and the number of iterations is reduced. Furthermore, this codec accommodates automatic repeat request (ARQ) scheme easily.

The IEEE 802.11 WLAN standards adopt CSMA/CA protocol with a backoff algorithm as medium access control technique. When the number of stations which attempt to access a network increases, the throughput efficiency of the standard goes down. In this paper, we propose a modified backoff algorithm which adaptively selects the Contention Window (CW) size according to the variation of the number of contending stations and present the results of simulation analysis.

In this study, we analyze the memory-based architecture of the FFT processor using the radix-4, and propose a novel mechanism that improves the throughput while simultaneously decreasing the area using single-port memories with several banks.

Tracking a large quantity of moving target tags simultaneously is essential for the localization and guidance of people in welfare facilities like hospitals and sanatoriums for the aged. The locating system using active RFID technology consists of a number of fixed RFID readers and tags carried by the target objects, or senior people. We compare the performances of several determination algorithms which use the power measurement of received signals emitted by the moving active RFID tags. This letter presents a study on the effect of collision in tracking large quantities of objects based on active RFID real time location system (RTLS). Traditional trilateration, fingerprinting, and well-known LANDMARC algorithm are evaluated and compared with varying number of moving tags through the SystemC-based computer simulation. From the simulation, we show the tradeoff relationship between the number of moving tags and estimation accuracy.

Bluetooth is a system for providing short-range, small size, low-power and low-cost connectivity operating in the ISM (Industrial Scientific Medicine) band at 2.4 GHz. Bluetooth has been seen as a promising candidate for ad-hoc wireless networking and wireless personal area network (WPAN). In this paper, we first discuss previously proposed polling algorithms in Bluetooth piconet. We then propose an efficient fair scheduling algorithm which improves the throughput efficiency of the system by adaptively assigning the polling interval according to the number of inactive slaves. We also show the simulation results of the proposed algorithm compared with previously proposed algorithms.

In this paper, a new implementation of the Viterbi decoder is proposed. The Modified State-Mapping VD algorithm combines the TB algorithm with the RE algorithm. By updating the starting point of the state for each memory bank, and by using Trace Back and Trace Forward information, LIFO (Last Input First Output) operation can be eliminated, which reduces the latency of the TB algorithm and decreases the resource usage of the RE algorithm. When the memory unit is 3, the resource usage is 13184 bits and the latency is 54 clocks. The latency of the proposed algorithm is 25% smaller than the MRE algorithm and 50% smaller than the k-pointer even TB algorithm. In addition, resource usage is 50% smaller than the RE algorithm. The resource usage is a little larger than that of the MRE algorithm for the small value of k, but it becomes smaller after k is larger than 16.

In the recent draft of the 802.11e MAC, the Hybrid Coordinator (HC) gives transmission opportunity (TXOP) for a station to transmit burst frames in TXOP for improving throughput efficiency. In this paper, we express the expected throughput for the Block Ack policy in Polled TXOP as a closed form function of the number of burst MSDUs, the number of fragmented MPDUs, the data payload length, the frame retry count, the wireless channel condition, and the selected PHY mode. Based on our simulation study and analysis, we show that the TXOP and proper Ack policy can enhance system performance, and that there are the Block Ack efficient block size and frame length to transmit the burst frames for each PHY mode. Moreover, we also show that when the Block Ack mechanism is combined with link adaptation, it has better throughput performance.

In medium access control (MAC) protocols for wireless local area networks (WLANs), the Round-Robin scheme is the general polling scheme. A major drawback of this scheme is that it is inefficient when only a small number of stations have packets to transmit. This inefficiency is caused by polling stations that have no packets to transmit. This paper proposes an effective and simple polling scheme to reduce the number of polling times for a station with no packets to transmit. For example, the simulation result shows that the throughput increases by 35.8% when fifteen stations out of thirty stations in the polling list have packets to transmit at IEEE 802.11a 54 Mbps rate.

The increased complexity in system design has brought an explosive growth in functional verification time. Thus, many verification methodologies have been proposed to reduce it. One of them is the co-emulation method in which the hardware accelerator and software simulator work together. This paper presents an effective testbench architecture for accelerated verification and reuse of parts of the testbench in co-emulation. The testbench is divided into a synthesizable part which can be hardware accelerated and a non-synthesizable part which remains on the software simulator. The split blocks of the testbench can be reused in other test environments. Experiments with real world systems show that the proposed verification environment has over 31% higher performance than that of the conventional co-emulation environment.

This paper presents a reconfigurable multi-band class E power amplifier designed in CMOS technology. The proposed class E power amplifier operates efficiently over sparsely separated frequency bands by switching the capacitance of the load network. Simulation results showed a stable and high power added efficiency of 60% with 18.5 dB gain, and 83% with 14.5 dB gain for 2.4 GHz and 5 GHz WLAN applications, respectively.