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Taekyu KIM Jin LEE Seungbeom LEE Sin-Chong PARK
Tracking a large quantity of moving target tags simultaneously is essential for the localization and guidance of people in welfare facilities like hospitals and sanatoriums for the aged. The locating system using active RFID technology consists of a number of fixed RFID readers and tags carried by the target objects, or senior people. We compare the performances of several determination algorithms which use the power measurement of received signals emitted by the moving active RFID tags. This letter presents a study on the effect of collision in tracking large quantities of objects based on active RFID real time location system (RTLS). Traditional trilateration, fingerprinting, and well-known LANDMARC algorithm are evaluated and compared with varying number of moving tags through the SystemC-based computer simulation. From the simulation, we show the tradeoff relationship between the number of moving tags and estimation accuracy.
Youngju DO Seungbeom LEE Sin-Chong PARK
In this paper, we design and implement a multi-protocol 13.56 MHz reader in software. In order to satisfy the timing constraint, three level optimizations called compile level, syntax level, and architectural level optimizations are applied. The execution time of optimized code is reduced by 85%, so that it satisfies timing requirement of a 60 MHz speed EISC processor. In addition, the binary code size is minimized to 211 KBytes which can be loaded on a 256 KB size memory.
This paper presents a novel high-speed low-complexity pipelined degree-computationless modified Euclidean (pDCME) algorithm architecture for high-speed RS decoders. The pDCME algorithm allows elimination of the degree-computation so as to reduce hardware complexity and obtain high-speed processing. A high-speed RS decoder based on the pDCME algorithm has been designed and implemented with 0.13-µm CMOS standard cell technology in a supply voltage of 1.1 V. The proposed RS decoder operates at a clock frequency of 660 MHz and has a throughput of 5.3 Gb/s. The proposed architecture requires approximately 15% fewer gate counts and a simpler control logic than architectures based on the popular modified Euclidean algorithm.