This paper presents a synthesizable testbench architecture based on a defined instruction for standalone mode verification. A set of instructions describes transitions of a signal. The set of instructions can be changed easily to describe different signal transitions by loading the different set of instructions on emulator's memory. The proposed testbench enables a fast emulation and increases flexibility and reusability by using an instruction set. To prove the performance of instruction based synthesizable testbench, we verified Bluetooth and IEEE 802.11a PHY baseband systems and compared their performance with those of co-sim mode and modified co-sim mode emulation.

Bluetooth is a system for providing short-range, small size, low-power and low-cost connectivity operating in the ISM (Industrial Scientific Medicine) band at 2.4 GHz. Bluetooth has been seen as a promising candidate for ad-hoc wireless networking and wireless personal area network (WPAN). In this paper, we first discuss previously proposed polling algorithms in Bluetooth piconet. We then propose an efficient fair scheduling algorithm which improves the throughput efficiency of the system by adaptively assigning the polling interval according to the number of inactive slaves. We also show the simulation results of the proposed algorithm compared with previously proposed algorithms.

In this paper, a new implementation of the Viterbi decoder is proposed. The Modified State-Mapping VD algorithm combines the TB algorithm with the RE algorithm. By updating the starting point of the state for each memory bank, and by using Trace Back and Trace Forward information, LIFO (Last Input First Output) operation can be eliminated, which reduces the latency of the TB algorithm and decreases the resource usage of the RE algorithm. When the memory unit is 3, the resource usage is 13184 bits and the latency is 54 clocks. The latency of the proposed algorithm is 25% smaller than the MRE algorithm and 50% smaller than the k-pointer even TB algorithm. In addition, resource usage is 50% smaller than the RE algorithm. The resource usage is a little larger than that of the MRE algorithm for the small value of k, but it becomes smaller after k is larger than 16.

The increased complexity in system design has brought an explosive growth in functional verification time. Thus, many verification methodologies have been proposed to reduce it. One of them is the co-emulation method in which the hardware accelerator and software simulator work together. This paper presents an effective testbench architecture for accelerated verification and reuse of parts of the testbench in co-emulation. The testbench is divided into a synthesizable part which can be hardware accelerated and a non-synthesizable part which remains on the software simulator. The split blocks of the testbench can be reused in other test environments. Experiments with real world systems show that the proposed verification environment has over 31% higher performance than that of the conventional co-emulation environment.

This paper proposes a fast algebraic codebook search for DSVD applications. In this method, the codebook search is simplified by reducing the number of possible position combinations using a mean-based track threshold multiplied by heuristically determined optimum threshold factor. And, to guarantee a complexity requirement of DSVD, the maximum number of searching position combinations is limited to 320. The proposed method reduced computational complexity considerably, compared with G.729 with a slight degradation of SNR. Particularly, it shows better speech quality with lower complexity than G.729A.

This paper presents a calibration scheme for delay mismatch between envelope and phase in the OFDM polar transmitter. An asynchronous delay detection method is proposed to avoid using a complicated signal processing algorithm or synchronous elements which need high clocking rates for detecting small delay mismatch. This scheme uses buffer delay chains to estimate the mismatch and then the estimated delay values are asynchronously stored in registers. It is verified that the proposed scheme well suites application to the OFDM polar transmitter through SPW, Matlab and HDL simulations. It achieves the margin of about 20 dB at 20 MHz offset, 10 dB at 40 MHz offset in terms of spectral limit specified in WLAN standard.