IEICE TRANSACTIONS on Communications
A High Throughput Medium Access Control Implementation Based on IEEE 802.11e Standard
Summary :
With the growing demand for high-performance multimedia applications over wireless channels, we need to develop a Medium Access Control (MAC) system that supports high throughput and quality of service enhancements. This paper presents the standard analysis, design architecture and design issues leading to the implementation of an IEEE 802.11e based MAC system that supports MAC throughput of over 100 Mbps. In order to meet the MAC layer timing constraints, a hardware/software co-design approach is adopted. The proposed MAC architecture is implemented on the Xilinx Virtex-II Pro Field-Programmable Gate Array (FPGA) (XC2VP70-5FF1704C) prototype, and connected to a host computer through an external Universal Serial Bus (USB) interface. The total FPGA resource utilization is 11,508 out of 33,088 (34%) available slices. The measured MAC throughput is 100.7 Mbps and 109.2 Mbps for voice and video access categories, transmitted at a data rate of 260 Mbps based on IEEE 802.11n Physical Layer (PHY), using the contention-based hybrid coordination function channel access mechanism.
- Publication
- IEICE TRANSACTIONS on Communications Vol.E93-B No.4 pp.948-960
- Publication Date
- 2010/04/01
- Publicized
- Online ISSN
- 1745-1345
- DOI
- 10.1587/transcom.E93.B.948
- Type of Manuscript
- PAPER
- Category
- Terrestrial Radio Communications
Authors
Keyword
IEEE 802.11e, MAC, EDCA, FPGA
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Min Li HUANG, Jin LEE, Hendra SETIAWAN, Hiroshi OCHI, Sin-Chong PARK, "A High Throughput Medium Access Control Implementation Based on IEEE 802.11e Standard" in IEICE TRANSACTIONS on Communications,
vol. E93-B, no. 4, pp. 948-960, April 2010, doi: 10.1587/transcom.E93.B.948.
Abstract: With the growing demand for high-performance multimedia applications over wireless channels, we need to develop a Medium Access Control (MAC) system that supports high throughput and quality of service enhancements. This paper presents the standard analysis, design architecture and design issues leading to the implementation of an IEEE 802.11e based MAC system that supports MAC throughput of over 100 Mbps. In order to meet the MAC layer timing constraints, a hardware/software co-design approach is adopted. The proposed MAC architecture is implemented on the Xilinx Virtex-II Pro Field-Programmable Gate Array (FPGA) (XC2VP70-5FF1704C) prototype, and connected to a host computer through an external Universal Serial Bus (USB) interface. The total FPGA resource utilization is 11,508 out of 33,088 (34%) available slices. The measured MAC throughput is 100.7 Mbps and 109.2 Mbps for voice and video access categories, transmitted at a data rate of 260 Mbps based on IEEE 802.11n Physical Layer (PHY), using the contention-based hybrid coordination function channel access mechanism.
URL: https://global.ieice.org/en_transactions/communications/10.1587/transcom.E93.B.948/_p
Copy
@ARTICLE{e93-b_4_948,
author={Min Li HUANG, Jin LEE, Hendra SETIAWAN, Hiroshi OCHI, Sin-Chong PARK, },
journal={IEICE TRANSACTIONS on Communications},
title={A High Throughput Medium Access Control Implementation Based on IEEE 802.11e Standard},
year={2010},
volume={E93-B},
number={4},
pages={948-960},
abstract={With the growing demand for high-performance multimedia applications over wireless channels, we need to develop a Medium Access Control (MAC) system that supports high throughput and quality of service enhancements. This paper presents the standard analysis, design architecture and design issues leading to the implementation of an IEEE 802.11e based MAC system that supports MAC throughput of over 100 Mbps. In order to meet the MAC layer timing constraints, a hardware/software co-design approach is adopted. The proposed MAC architecture is implemented on the Xilinx Virtex-II Pro Field-Programmable Gate Array (FPGA) (XC2VP70-5FF1704C) prototype, and connected to a host computer through an external Universal Serial Bus (USB) interface. The total FPGA resource utilization is 11,508 out of 33,088 (34%) available slices. The measured MAC throughput is 100.7 Mbps and 109.2 Mbps for voice and video access categories, transmitted at a data rate of 260 Mbps based on IEEE 802.11n Physical Layer (PHY), using the contention-based hybrid coordination function channel access mechanism.},
keywords={},
doi={10.1587/transcom.E93.B.948},
ISSN={1745-1345},
month={April},}
Copy
TY - JOUR
TI - A High Throughput Medium Access Control Implementation Based on IEEE 802.11e Standard
T2 - IEICE TRANSACTIONS on Communications
SP - 948
EP - 960
AU - Min Li HUANG
AU - Jin LEE
AU - Hendra SETIAWAN
AU - Hiroshi OCHI
AU - Sin-Chong PARK
PY - 2010
DO - 10.1587/transcom.E93.B.948
JO - IEICE TRANSACTIONS on Communications
SN - 1745-1345
VL - E93-B
IS - 4
JA - IEICE TRANSACTIONS on Communications
Y1 - April 2010
AB - With the growing demand for high-performance multimedia applications over wireless channels, we need to develop a Medium Access Control (MAC) system that supports high throughput and quality of service enhancements. This paper presents the standard analysis, design architecture and design issues leading to the implementation of an IEEE 802.11e based MAC system that supports MAC throughput of over 100 Mbps. In order to meet the MAC layer timing constraints, a hardware/software co-design approach is adopted. The proposed MAC architecture is implemented on the Xilinx Virtex-II Pro Field-Programmable Gate Array (FPGA) (XC2VP70-5FF1704C) prototype, and connected to a host computer through an external Universal Serial Bus (USB) interface. The total FPGA resource utilization is 11,508 out of 33,088 (34%) available slices. The measured MAC throughput is 100.7 Mbps and 109.2 Mbps for voice and video access categories, transmitted at a data rate of 260 Mbps based on IEEE 802.11n Physical Layer (PHY), using the contention-based hybrid coordination function channel access mechanism.
ER -
English
