IEICE TRANSACTIONS on Fundamentals
A Low-Jitter Delay-Locked Loop with Harmonic-Lock Prevention
Summary :
A multiphase low-jitter delay-locked loop (DLL) with harmonic-lock prevention, targeted at a gigabit parallel link interface, is delineated. A three-input four-state dynamic phase detector (PD) is proposed to obviate harmonic locking. Employing a low-jitter delay element and a new type of PD, the DLL is compact and feasible in its nature. The DLL is designed using a 0.35 µm 2P4M CMOS process with 3.3 V supply. Experimental results show that the circuit avoids false locking.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E85-A No.2 pp.505-507
- Publication Date
- 2002/02/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- LETTER
- Category
- Circuit Theory
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Sungkyung PARK, Changsik YOO, Sin-Chong PARK, "A Low-Jitter Delay-Locked Loop with Harmonic-Lock Prevention" in IEICE TRANSACTIONS on Fundamentals,
vol. E85-A, no. 2, pp. 505-507, February 2002, doi: .
Abstract: A multiphase low-jitter delay-locked loop (DLL) with harmonic-lock prevention, targeted at a gigabit parallel link interface, is delineated. A three-input four-state dynamic phase detector (PD) is proposed to obviate harmonic locking. Employing a low-jitter delay element and a new type of PD, the DLL is compact and feasible in its nature. The DLL is designed using a 0.35 µm 2P4M CMOS process with 3.3 V supply. Experimental results show that the circuit avoids false locking.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e85-a_2_505/_p
Copy
@ARTICLE{e85-a_2_505,
author={Sungkyung PARK, Changsik YOO, Sin-Chong PARK, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Low-Jitter Delay-Locked Loop with Harmonic-Lock Prevention},
year={2002},
volume={E85-A},
number={2},
pages={505-507},
abstract={A multiphase low-jitter delay-locked loop (DLL) with harmonic-lock prevention, targeted at a gigabit parallel link interface, is delineated. A three-input four-state dynamic phase detector (PD) is proposed to obviate harmonic locking. Employing a low-jitter delay element and a new type of PD, the DLL is compact and feasible in its nature. The DLL is designed using a 0.35 µm 2P4M CMOS process with 3.3 V supply. Experimental results show that the circuit avoids false locking.},
keywords={},
doi={},
ISSN={},
month={February},}
Copy
TY - JOUR
TI - A Low-Jitter Delay-Locked Loop with Harmonic-Lock Prevention
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 505
EP - 507
AU - Sungkyung PARK
AU - Changsik YOO
AU - Sin-Chong PARK
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E85-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2002
AB - A multiphase low-jitter delay-locked loop (DLL) with harmonic-lock prevention, targeted at a gigabit parallel link interface, is delineated. A three-input four-state dynamic phase detector (PD) is proposed to obviate harmonic locking. Employing a low-jitter delay element and a new type of PD, the DLL is compact and feasible in its nature. The DLL is designed using a 0.35 µm 2P4M CMOS process with 3.3 V supply. Experimental results show that the circuit avoids false locking.
ER -
English
