Much has been said and written about the changes in analog IC technology such as shrinking line widths, vanishingly low supply voltages, severe power limitations, and digital noise. But beyond these technology changes and their subsequent methodology changes, a far more subtle revolution is happening in the nature of the profession itself. Technology, software, and product evolution have all conspired to create a new kind of analog IC designer, one very different from the IC designers of the past.

A 2-GHz down-converter for wide-band wireless communication systems is described. To achieve both wide-band output characteristic and LO signal suppression, an on-chip LC series resonator which is resonated at LO signal frequency and a transimpedance amplifier which is used in the output buffer circuit are used. To achieve a low sensitivity to temperature, two kinds of bias circuits; a V_T reference current source and a bandgap reference current source are used. The measured 3-dB bandwidth of 600 MHz is achieved. The conversion gain varies less than 0.2 dB within 200 MHz 10 MHz and 400 MHz 10 MHz band and 0.7 dB for the temperature range from -34 to 85. At room temperature, conversion gain of 15 dB, NF of 9.5 dB and IIP3 of -5 dBm are obtained respectively. The down-converter is fabricated using Si BiCMOS process with f_t=20 GHz, and it occupies approximately 1 mm².

A 1-V 2-GHz receiver that exhibits an image rejection of 49 dB is described. It consists of a low-noise amplifier, a quadrature mixer and on-chip polyphase filters, and was fabricated by 0.2-µm fully depleted CMOS/SIMOX technology. The quadrature mixer employs an LC-tuned folded structure with a common RF input for I and Q channels. This enables 1-V operation, suppresses phase errors in LO signals, and improves the image-rejection performance by about 15-dB compared to a conventional quadrature architecture. The current source of the single-to-balance converter at the mixer input consists of a transistor and an LC tank in a cascode configuration. This enhances its output impedance and improves its common-mode-rejection ratio (CMRR) and the IIP2 characteristics of the receiver. The chip consumes 12 mW with 1-V power supply. The receiver provides an NF of 10 dB with an IIP3 of -15.8 dBm and IIP2 of 12.3 dBm.

This paper describes 2.4-GHz-band front-end building circuits--a down conversion mixer (DCM), a dual-modulus divide-by-4/5 prescaler, a transmit/receive antenna switch (SW), a power amplifier (PA), and a low noise amplifier (LNA). They are fabricated using a standard bulk 0.18 µm CMOS process with a lower current consumption than bipolar circuits, and can operate at the low supply voltage of 1.8 V. Meshed-shielded pads are adopted for lower receiver circuit noise. Pads shielded by metals become cracked when they are bounded, therefore silicided active areas are used as shields instead of metals to avoid these cracks. The meshed shields achieve lower parasitic pad capacitors without parasitic resistors, and also act as dummy active areas. The proposed DCM has a high IP3 characteristic. The DCM has a cascode FET configuration and LO power is injected into the lower FET. By keeping the drain-source voltage of the upper transistor large, the nonlinearity of the drain-source transconductance is reduced and a low distortion DCM is realized. It achieves a higher input referred IP3 with a higher conversion gain for almost the same current consumption of a conventional single-balanced mixer. The output referred IP3 is higher 5.0 dB than the single-balanced mixer. The proposed dual-modulus prescaler employs a fully-differential technique to achieve stable operation. In order to avoid errors, the fully-differential circuit gives the logic voltage swing margins. In addition, the differential technique also reduces the noise effect from the supply voltage line because of the common-mode signal rejection. The maximum operating frequency is 3.0 GHz, and the one flip-flop power consumption normalized by the maximum operating frequency is 180 µW/GHz.

In this paper, we discuss an IF image rejection system with variable bandwidth and center frequency. The system is consists of a pair of frequency mixers multiplied by the complex sinusoid and a complex analog filter. By employing the complex leapfrog structure using OTA-C configuration and the frequency transformation from the normalized LPF, the proposed system is capable of variable bandwidth and center frequency characteristics. SPICE simulations result more than 43 [dB] image rejection is achieved for 6 [kHz] and 12 [kHz] bandwidths at 50 [kHz] IF.

In this paper, we propose a universal biquad filter that can realize all types of 2nd-order functions, such as Low-pass Filters (LPF), High-Pass Filters (HPF), Band-Pass Filters (BPF), Band-Elimination Filters (BEF), and All-Pass Filters (APF). Also, the filter types can be programmable digitally with built-in switches. The proposed circuit can be realized by using a CMOS technology that is suitable for a mixed digital-analog LSI. In addition, the circuit can operate in high frequencies with a low power supply voltage because it is based on a current-mode circuit. Finally, the proposed circuit is simulated by PSpice to confirm its characteristics.

A cascode crystal oscillator is widely used for the stable frequency source of mobile communication equipments. Recently, IC production of the cascode crystal oscillator has become necessary. The cascode crystal oscillator is composed of a colpitts crystal oscillator and a cascode connected base-common buffer amplifier. The base bypass condenser prevents the area size reduction. In this paper, we have proposed the new structures of the cascode crystal oscillator suitable for integrated circuits. The proposed circuits have the advantages on reduction of the area size and start-up time without deteriorating the frequency stability against the load impedance variation and other performances. The simulation and experiment have shown the effectiveness of the proposed circuits.

A highly stable oven-controlled crystal oscillator (OCXO) with low phase-noise characteristics has been developed using a dual-mode SC-cut quartz crystal oscillator. The OCXO uses a conventional oven-control system for coarse compensation and a digital-correction system, which uses B-mode signal in an SC-cut resonator as a temperature sensor, for fine compensation. Combining these two forms of compensation greatly improves the stability of the C-mode frequency without requiring a double-oven system. The experimental results indicated that the frequency stability of the proposed OCXO, including the frequency-temperature hysteresis, is ten times better than that of a conventional, free-running OCXO. The results also indicated that the proposed OCXO has good frequency retraceability and low phase-noise characteristics.

This paper presents an explicit analysis of the output error power in wideband sampling systems with finite aperture time in the presence of sampling jitter. Sampling jitter and finite aperture time affect the ability of wideband sampling systems to capture high-frequency signals with high precision. Sampling jitter skews data acquisition timing points, which causes large errors in high-frequency (large slew rate) signal acquisition. Finite sampling-window aperture works as a low pass filter, and hence it degrades the high-frequency performance of sampling systems. In this paper, we discuss these effects explicitly not only in the case that either sampling jitter or finite aperture time exists but also the case that they exist together, for any aperture window function (whose Fourier transform exists) and sampling jitter of Gaussian distribution. These would be useful for the designer of wideband sampling data acquisition systems to know how much sampling jitter and aperture time are tolerable for a specified SNR. Some experimental measurement results as well as simulation results are provided as validation of the analytical results.

A building block for widening an input range under low power-supply voltages is proposed and the block is used in a popular linearization technique for voltage-to-current converters. The block employs two MOSFETs each of which actively works when and only when the other is in cutoff region. Accurate level shift circuits for the control of the MOSFETs enable such exclusive operation. Simulation results show that the complementary MOSFETs perform as an equivalent MOSFET without any cutoff region. It is also confirmed that the novel linear voltage-to-current converter is effective for not only a wide input range but also low-power consumption.

This paper proposes a novel method to realize an input stage for a rail-to-rail operational transconductance amplifier (OTA). The proposed input stage consists of single channel type MOSFETs. Therefore no matching is necessary between n-channel MOSFETs and p-channel MOSFETs unlike conventional methods. The proposed input stage is composed of three MOSFETs which operate in plural operation regions. Nevertheless a combination of drain currents of the three MOSFETs is proportional to an input voltage which varies between two power-supply rails. A circuit configuration to realize a rail-to-rail OTA with the proposed input stage is also proposed. The operation principle and the validity of the proposed circuit are confirmed through HSPICE simulations.

The analog inverter for realization of the NOT function is the indispensable circuit element in the voltage-mode analog and digital signal processing. In this paper, we propose a novel analog inverter composed of only two neuron-MOS transistors. The analog inverter has the weighted negative feedback mechanism to operate both of neuron-MOS transistors under the saturation region in all input ranges. In verification using HSPICE simulations, the analog inverter performs the high linearity with errors of approximately 40 [mV] in all input ranges, particularly errors of less than 19 [mV] in more than 90% of input ranges. And, the maximum power consumption of the analog inverter is less than 1.5 [µW] although a peak of a standard CMOS inverter is around 30 [µW] under the supply voltage of 3.0 [V]. These good stability and results are produced by the negative feedback. Furthermore, fabrication costs of the analog inverters can be kept at the minimum because neuron-MOS transistors can be actualized in a conventional CMOS process without any additional process. For applications of the analog inverter, the voltage comparator with high noise margins is designed and is applied to the two-input MAX and the two-input MIN circuits in the voltage-mode. The MAX and the MIN circuits for realization of the MAX and the MIN functions, respectively, can be composed of total ten transistors each. They also perform well in verifications. On the basis of the proposed circuits, almost all of voltage-mode multi-valued logic circuits with high-performance can be realized like present binary logic systems. And, the proposed circuits can give full play to the high linearity and advantages for the arbitrary transformation of signal forms in the analog signal processing such as the fuzzy control.

The power supply voltage of LSI has been lowered due to system requirements for low power dissipation. An on-chip power-on reset pulse generator (POR-PG) is used to determine the initial state of the memory devices of the system LSI. The requirement for the POR-PG is strict for lower power supply voltage because noise margin is smaller relatively. This paper describes a POR-PG for low power voltage supply (V_dd) which overcomes these problems. Hardware measurement proves improved pulse height relative to various power-on profiles (slope, rise time etc.) and fluctuations of temperature and process. Further, the design provides robust noise immunity against voltage fluctuations on the power supply line. The circuit is implemented within a small area (115 µm 345 µm) in the input/output buffer area of a micro-processor and hard-disk controller integrated LSI with 0.25-µm four-layer-metal CMOS technology.

A fully on-chip active guard band circuit is proposed. The proposed circuit is mainly composed of current mirrors and based on a DC bias technique. HSPICE simulations and experiment results confirm the validity of the proposed active guard band circuit.

This paper proposes a new method for image segmentation and extraction using nonlinear cellular networks. Flexible segmentation of complicated natural scene images is achieved by using resistive-fuse networks, and each segmented regions is extracted by nonlinear oscillator networks. We also propose a nonlinear cellular network circuit implementing both resistive-fuse and oscillator dynamics by using pulse-modulation techniques. The basic operation of the nonlinear network circuit is confirmed by SPICE simulation. Moreover, the 1010-pixel image segmentation and extraction are demonstrated by high-speed circuit simulation.

A number of studies have recently been published concerning chaotic neuron models and asynchronous neural networks having chaotic neuron models. In the case of large-scale neural networks having chaotic neuron models, the neural network should be constructed using analog hardware, rather than by computer simulation via software, due to the high speed and high integration of analog circuits. In the present study, we discuss the circuit structure of a chaotic neuron model, which is constructed on the basis of the mathematical model of an asynchronous chaotic neuron. We show that the pulse-type hardware chaotic neuron model can be constructed on the basis of the mathematical model of an asynchronous chaotic neuron. The proposed model is an effective model for the cell body section of the pulse-type hardware chaotic neuron model for ICs. In addition, we show the bifurcation structure of our composed model, and discuss the bifurcation routes and return maps thereof.

This letter presents a novel application of the Verilog-A, which is a hardware description language for analog circuits, to the modeling and simulation of high-speed interconnects in time/frequency transform-domain for signal integrity problems. This modeling method with the Verilog-A language would handle the transfer function approximation and admittance matrices, which are expressed by the dominant poles and residues as used in AWE technique. Finally, it is shown that modeling and simulation of the high-speed interconnects with nonlinear terminations can be done easily.

In this report, we propose a new bilateral floating resistor circuit having both positive and negative resistance values. The equivalent resistance of this floating resistor in CMOS technology can be changed by using controlled-voltages, which is an advantage over polysilicon or diffused resistor in the integrated circuit. Moreover the characteristics of the proposed circuit are independent of the threshold voltage. We have simulated the proposed circuit by using HSPICE. Finally, we have confirmed that the proposed circuit is useful as an analog component.

In this paper, we propose a bit-rate adaptive coding system based on lossless DCT (L-DCT). Our adaptive coding system consists of three different operation modes: lossless, near-lossless and lossy coding modes. Quantization is applied in transform domain (after the L-DCT) and spatial domain (before the L-DCT) in lossy mode and near-lossless mode, respectively. Our adaptive coding system can automatically select its operation mode at a given bit rate because it contains a function to calculate the turning point between near-lossless mode and lossy mode from characteristic of input signal. Existence of the turning point is mathematically proved in this paper. Simulation results confirm not only effectiveness of our adaptive coding system but also accuracy of our theoretical analysis.

This paper proposes an extension of a conventional current conveyor (CC) concept and its applications. A relaxation of the definition of a conventional CC makes a CC simple. A novel current conveyor named extended current conveyor (ECC) is introduced. An ECC keeps the most significant feature of a CC, i.e., a CC is combination of a VCVS and a CCCS. On the other hand, the other conditions are relaxed. All terminals of the ECC are allowed to have offset voltage and offset current. An ECC usually has a simple structure with a small number of MOSFETs thanks to the relaxation of the conditions. Some circuit configurations for the ECC which have various characteristics are shown. An NIC and OTAs are realized using ECCs. Validity of an ECC is confirmed through HSPICE simulation.

We present a state-space approach to the problem of designing a parallel feedforward compensator (PFC), which has the same dimension of the input i.e. input-dimensional, for a class of non-square linear systems such that the closed-loop system is strictly passive. For a non-minimum phase system or a system with high relative degree, passification of the system cannot be achieved by any other methodologies except by using a PFC. In our scheme, we first determine a squaring gain matrix and an additional dynamics that is connected to the system in a feedforward way, then a static passifying control law is designed. Consequently, the actual feedback controller will be the static control law combined with the feedforward dynamics. Necessary and sufficient conditions for the existence of the PFC are given by the static output feedback formulation, which enables to utilize linear matrix inequality (LMI). Since the proposed PFC is input-dimensional, our design procedure can be viewed as a solution to the low-order dynamic output feedback control problem in the literature. The effectiveness of the proposed method is illustrated by some numerical examples.

In this study, a hybrid genetic algorithm/neural network with fuzzy logic controller (NN-flcGA) is proposed to find the global optimum of reliability assignment/redundant allocation problems which should be simultaneously determined two different types of decision variables. Several researchers have obtained acceptable and satisfactory results using genetic algorithms for optimal reliability assignment/redundant allocation problems during the past decade. For large-size problems, however, genetic algorithms have to enumerate numerous feasible solutions due to the broad continuous search space. Recently, a hybridized GA combined with a neural network technique (NN-hGA) has been proposed to overcome this kind of difficulty. Unfortunately, it requires a high computational cost though NN-hGA leads to a robuster and steadier global optimum irrespective of the various initial conditions of the problems. The efficacy and efficiency of the NN-flcGA is demonstrated by comparing its results with those of other traditional methods in numerical experiments. The essential features of NN-flcGA namely, 1) its combination with a neural network (NN) technique to devise initial values for the GA, 2) its application of the concept of a fuzzy logic controller when tuning strategy GA parameters dynamically, and 3) its incorporation of the revised simplex search method, make it possible not only to improve the quality of solutions but also to reduce computational cost.

A Wireless Sensor Network (WSN, for short) is a distributed system consisting of n sensor nodes and a base station. In this paper, we propose an energy-efficient protocol to initialize the sensor nodes in a WSN, that is, to assign a unique ID to each sensor node. We show that if an upper bound u on the number n of sensor nodes is known beforehand, for any f 1 and any small µ (0<µ<1), a WSN without collision detection capability can be initialized in O((log (1/µ) + log f)u^1+µ) time slots, with probability exceeding 1-(1/f), with no sensor node being awake for more than O(log (1/µ)+ log f) time slots.

In this paper, we investigate self diagnosable systems on multi-processor systems, known as one-step t-diagnosable systems introduced by Preparata et al. Kohda has proposed "highly structured system" to design diagnosable systems such that faulty processors are diagnosed efficiently. On the other hand, it is known that Cayley graphs have been investigated as good models for architectures of large-scale parallel processor systems. We investigate some conditions for Cayley graphs to be topologies for optimal highly structured diagnosable systems, and present several examples of optimal diagnosable systems represented by Cayley graphs.

Watermarking techniques are widely used to protect the secret document. In some valuable literatures, most of them concentrate on the binary data watermarking by using comparisons of an original image and a watermarked image to extract the watermark. In this paper, an efficient watermarking algorithm is presented with two-layer hidden for gray-level image watermarking. In the first layer, the key information is found based on the codebook concept. Then the secret key is further hidden to the watermarked image adopting the encryption consisting of spatial distribution in the second layer. The simulations demonstrate that the watermarking information is perceptually invisible in the watermarked image. Moreover, the gray-level watermark can be extracted by referring key parameters rather than the original image, and the extracting quality is very good.

Recently, Kasahara and Murakami proposed new product-sum type public-key cryptosystems with the Chinese remainder theorem, Methods B-II and B-IV. They also proposed a new technique of selectable encryption key, which is referred to as 'Home Page Method (HP Method).' In this paper, first, we describe Methods B-II and B-IV. Second, we propose an effective attack for Method B-II and discuss the security of Methods B-II and B-IV. Third, applying the HP Method to Methods B-II and B-IV, we propose new product-sum type PKC with selectable encryption key. Moreover, we discuss the security of the proposed cryptosystems.

A traitor tracing scheme is a broadcast encryption scheme in which a provider can trace malicious authorized users who illegally gave their personal keys to unauthorized users. The conventional schemes have some problems; one of them is that there exists an upper bound on the sizes of keys to certify the security of the scheme against a collusion attack by many traitors, and so that the size of the header increases according to the increase of the bound. We shall propose a new traitor tracing scheme where the header size is independent of the number of traitors.

Y. S. Han et al. have proposed an efficient maximum likelihood decoding (MLD) algorithm using A^* algorithm which is the graph search method. In this paper, we propose a new MLD algorithm for linear block codes. The MLD algorithm proposed in this paper improves that given by Han et al. utilizing codewords of dual codes. This scheme reduces the number of generated codewords in the MLD algorithm. We show that the complexity of the proposed decoding algorithm is reduced compared to that given by Han et al. without increasing the probability of decoding error.

Semiconductor memories are highly vulnerable to adjacent double bit errors for two reasons: 1) The bombardment of strong radioactive particles such as cosmic particles on DRAM chips and data bit lines. 2) The coupling noise in recent high density DRAM chips due to the wiring capacitance between two adjacent data bit lines. In addition, byte errors which result from entire chip failures are also a source of concern. Under this situation, codes capable of correcting adjacent double bit errors and simultaneously detecting single byte errors are suitable for application in semiconductor memory systems. This paper proposes two classes of codes called Adjacent Double bit Error Correcting-Single b-bit Byte Error Detecting (ADEC-S_bED) codes and Adjacent Double bit within a b-bit byte Error Correcting-Single b-bit byte Error Detecting ((ADEC)_b-S_bED) codes. For the practical case where byte length is 4 bits, the proposed codes require at most one extra check bit than their bounds. Furthermore, the number check bits required by the proposed (ADEC)₄-S₄ED code is same as that of the well known SEC-DED code for practical information bit lengths such as 64, 128, 256, etc.

A near-optimum parallel algorithm for bipartite subgraph problem using gradient ascent learning algorithm of the Hopfield neural networks is presented. This parallel algorithm, uses the Hopfield neural network updating to get a near-maximum bipartite subgraph and then performs gradient ascent learning on the Hopfield network to help the network escape from the state of the near-maximum bipartite subgraph until the state of the maximum bipartite subgraph or better one is obtained. A large number of instances have been simulated to verify the proposed algorithm, with the simulation result showing that our algorithm finds the solution quality is superior to that of best existing parallel algorithm. We also test the proposed algorithm on maximum cut problem. The simulation results also show the effectiveness of this algorithm.

A multiphase low-jitter delay-locked loop (DLL) with harmonic-lock prevention, targeted at a gigabit parallel link interface, is delineated. A three-input four-state dynamic phase detector (PD) is proposed to obviate harmonic locking. Employing a low-jitter delay element and a new type of PD, the DLL is compact and feasible in its nature. The DLL is designed using a 0.35 µm 2P4M CMOS process with 3.3 V supply. Experimental results show that the circuit avoids false locking.

We introduce PC Linux cluster computing techniques to an Evolutionary Graph Generation (EGG) system, and successfully implement the parallel version of the EGG system, called PEGG. Our survey satisfactorily shows that the parallel evolutionary approach meets our expectation that the final solutions obtained from PEGG will be as good as or better than those obtained from EGG, and that PEGG can ultimately improve the speed of evolution.

Existing byte error control codes require too many check bits if applied to a memory system that uses recent semiconductor memory chips with wide I/O data such as 16 or 32 bits, i.e., b=16 or 32. On the other hand, semiconductor memory chips are highly vulnerable to random double bit within a memory chip errors when they are used in some applications, such as satellite memory systems. Under this situation, it becomes necessary to design suitable new codes with double bit within a chip error correcting capability for computer memory systems. This correspondence proposes a class of codes called Double bit within a block Error Correcting - Single b-bit byte Error Correcting ((DEC)_B-S_bEC) codes where block and byte correspond to memory chip and memory sub-array data outputs, respectively. The proposed codes provide protection from both random double bit errors and single sub-array data faults. For most of the practical cases, the (DEC)_B-S_bEC codes presented in this correspondence have the capability of accommodating the check bits in a single dedicated memory chip.

In this letter, sampling and quantizer design for the Gaussian detection problem are considered. A constraint on the transmission rate from the remote sensor to the optimal discrete detector is assumed. The trade-off between sampling rate and the number of quantization levels is studied and illustrated by means of an example.

A method of learning for multi-layer artificial neural networks is proposed. The learning model is designed to provide an effective means of escape from the Backpropagation local minima. The system is shown to escape from the Backpropagation local minima and be of much faster convergence than simulated annealing techniques by simulations on the exclusive-or problem and the Arabic numerals recognition problem.