Semiconductor memories are highly vulnerable to adjacent double bit errors for two reasons: 1) The bombardment of strong radioactive particles such as cosmic particles on DRAM chips and data bit lines. 2) The coupling noise in recent high density DRAM chips due to the wiring capacitance between two adjacent data bit lines. In addition, byte errors which result from entire chip failures are also a source of concern. Under this situation, codes capable of correcting adjacent double bit errors and simultaneously detecting single byte errors are suitable for application in semiconductor memory systems. This paper proposes two classes of codes called Adjacent Double bit Error Correcting-Single b-bit Byte Error Detecting (ADEC-SbED) codes and Adjacent Double bit within a b-bit byte Error Correcting-Single b-bit byte Error Detecting ((ADEC)b-SbED) codes. For the practical case where byte length is 4 bits, the proposed codes require at most one extra check bit than their bounds. Furthermore, the number check bits required by the proposed (ADEC)4-S4ED code is same as that of the well known SEC-DED code for practical information bit lengths such as 64, 128, 256, etc.

In certain computer and communication systems, the significant number of byte errors are not hard errors, but a few transient bit errors confined to byte regions. This kind of byte errors are called spotty byte errors, meaning, not all, but only 2 or 3 random bits, are corrupted in a byte. Especially, the codewords of memory systems which use recent high density wide I/O data semiconductor DRAM chips are prone to this kind of spotty byte errors. This is because, the presence of strong electromagnetic waves in the environment or the bombardment of an energetic particle on a DRAM chip is highly likely to upset more than just one bit stored in that chip. Under this situation, codes capable of correcting single spotty byte errors are suitable for application in semiconductor memory systems. This paper defines a spotty byte error as a random t-bit error confined to a b-bit byte and proposes a class of codes called Single t/b-error Correcting (St/bEC) codes which are capable of correcting single spotty byte errors occurring in computer and communication systems. For the case where the chip data output is 16 bits, i.e., b=16, the S3/16EC code proposed in this paper requires only 16 check bits, that is, only one chip is required for check bits at practical information lengths such as 64, 128 and 256 bits. Furthermore, this S3/16EC code is capable of detecting more than 95% of all single 16-bit byte errors at information length 64 bits.

Besides single byte errors which are caused by single chip failures, semiconductor memories used in some applications, such as satellite memory systems, are highly vulnerable to random double bit errors. It is therefore necessary to design Double bit Error Correcting--Single b-bit byte Error Correcting (DEC-SbEC) codes which correct both random double bit errors and single b-bit byte errors. This correspondence proposes a class of generic DEC-SbEC codes that are applicable to computer memory systems using recent high density DRAM chips with wide I/O data, such as, 8, 16 or 32 bits per chip. The proposed DEC-S8EC codes are suitable for memory systems using DRAM chips with 8-bit I/O data, and require 24 check bits for practical information lengths such as 64 and 128 bits.

Existing byte error control codes require too many check bits if applied to a memory system that uses recent semiconductor memory chips with wide I/O data such as 16 or 32 bits, i.e., b=16 or 32. On the other hand, semiconductor memory chips are highly vulnerable to random double bit within a memory chip errors when they are used in some applications, such as satellite memory systems. Under this situation, it becomes necessary to design suitable new codes with double bit within a chip error correcting capability for computer memory systems. This correspondence proposes a class of codes called Double bit within a block Error Correcting - Single b-bit byte Error Correcting ((DEC)B-SbEC) codes where block and byte correspond to memory chip and memory sub-array data outputs, respectively. The proposed codes provide protection from both random double bit errors and single sub-array data faults. For most of the practical cases, the (DEC)B-SbEC codes presented in this correspondence have the capability of accommodating the check bits in a single dedicated memory chip.