Data compression is popularly applied to computer systems and communication systems. Especially, lossless compression is applied to text compression. Since compressed data are very sensitive to errors, several error control methods for data compression using probability model, such as for arithmetic coding, have been proposed. This paper proposes to apply an unequal error protection, or a UEP, scheme to LZ77 coding and LZW coding. This investigates a structure of the compressed data and clarifies a part which is more sensitive to errors than the other by using theoretical analysis and computer simulation. The UEP scheme protects the error-sensitive part from errors more strongly than the others. Computer simulation says that the proposed scheme can recover from errors in the compressed data more effectively than the conventional methods.

Error control codes have extensively been applied to semiconductor memories using high density RAM chips with wide I/O data, e.g., with 8-bit or 16-bit I/O data. Recently, spotty byte errors called s-spotty byte errors are newly defined as t or fewer bits errors in a byte having length b bits, where 1 ≤ t ≤ b. This paper proposes another type of spotty byte errors, i.e., m-spotty byte errors, where more than t bits errors in a byte may occur due to hit by high energetic particles. For these errors, this paper presents generalized m-spotty byte error control codes with minimum m-spotty distance d.

The class of codes described in this paper is used for Single b-Adjacent bit-group Error Correction (SbEC). This is especially useful in large memory systems which use integrated semiconductor memory chips, each containing b-output bits. The proposed codes have odd-weight-column H-matrix characteristic and superior error detection capability, and facilitates the construction of modularized parallel high speed encoding / decoding network through rotational coding techniques. For a special case of b1, this class of codes is equivalent to the optimal odd-weight-column SEC-DED (Single Error Correcting - Double Error Detecting) codes. A computation indicates that the odd-weight-column SbEC codes have better error detection capability than the conventional SbEC codes.

Nonbinary M-ary data processed by data entry systems, such as keyboard devices and character recognition systems, often have various types of error, such as symbol-substitution errors, deletion errors, insertion errors, and adjacent-symbol-transposition errors. This paper proposes nonsystematic M-ary codes capable of correcting these errors. The code is defined as a set of codewords that satisfy three conditions required to correct substitution, deletion/insertion, and adjacent-symbol-transposition errors. Since symbol-substitution errors in data entry systems are usually asymmetric, this paper also presents asymmetric-symbol-substitution error correcting codes capable of correcting deletion, insertion, and adjacent-symbol-transposition errors. For asymmetric-symbol-substitution error correction, we employ a mapping derived from the vertex coloring in an error directionality graph. The evaluation shows that the asymmetric codes have three to five times larger number of codewords than the symmetric codes.

This paper proposes new design methods for single b-bit (b2) byte error correcting and double bit error detecting code, called SbEC-DED code, suitable for high-speed memory systems using byte organized RAM chips. This new type of byte error control code is practical from the viewpoint of having less redundancy and stronger error control capability than the existing ones. A code design method using elements from a coset of subfield under addition gives the practical SbEC-DED code with 64 information bits and 4-bit byte length which has the same check-bit length, 12 bits, as that of the Hamming single byte error correcting code. This also has very high error detection capabilities of random double byte errors and of random triple bit errors.

Unidirectional/Asymmetric error control codes have extensively been studied, not only from theoretical interest but from application to computer systems or communication systems. Recently, attention has been focused on detecting only d, not all, unidirectional errors, that is, d bits unidirectional error ditecting (d-UED) codes. Borden proposed an optimal nonsystematic d-UED code. This paper shows a new design method for cost-effective self-testing checker for the optimal d-UED code. The checking policy is to check whether condition of the Borden code satisfies or not. The proposed checker includes the parallel weight counter, the comparator and th e modulo adder in which new residue operation is defined and hence this makes the circuit self-testing. These circuits are designed to have all possible input patterns in order to satisfy self-testing property. Finally, the proposed checker has greatly reduced hardware amount compared to the existing one.

Even though coding theory applications in fault tolerant computing started with Hamming code invention, their developments were made almost independently from those in information and communication theories after this initiation. This paper gives a brief overview on coding theory applications in fault tolerant computing. A more detailed survey was made on the most important recent developments. Since there are many items of mutual interest to engineers in both fields, mutual stimulations and cooperations between them would be highly appreciated for future mutual developments in coding theory applications.

Spotty byte error control codes are very effective for correcting/detecting errors in semiconductor memory systems using recent high-density RAM chips with wide I/O data, e.g., 8, 16, or 32 bits. A spotty byte error is defined as t-bit errors within a byte of length b-bit, where 1 ≤ t ≤ b, and denoted as t/b-error. This paper proposes a new error model of two spotty byte errors occurring simultaneously, i.e., t/b-error and t′/b-error, where t t′, called complex spotty byte errors. This paper presents two complex m-spotty byte error control codes, i.e., St/bEC-(St/b+St′/b)ED codes which correct all single t/b-errors and detect both t/b-errors and t′/b-errors simultaneously, and (St/b+St′/b)EC codes which correct both single t/b-errors and single t′/b-errors simultaneously. This paper also presents practical examples of the codes with parameter t′=1, that is, St/bEC-(St/b+S)ED codes and (St/b+S) EC codes which require smaller check-bit length than the existing Single t/b-error Correcting and Double t/b-error Detecting (St/bEC-Dt/bED) codes and the Double t/b-error Correcting (Dt/bEC) codes, respectively.

This paper presents a class of binary block codes capable of correcting single synchronization errors and single reversal errors with fewer check bits than the existing codes by 3 bits. This also shows a decoding circuit and analyzes its complexity.

This paper proposes a large capacity high-speed file memory system implemented with wafer scale RAM which adopts a novel defect-tolerant technique. Based on set-associative mapping, the defective memory blocks on the wafer are repaired by switching with the spare memory blocks. In order to repair the clustered defective blocks, these are permuted logically with other blocks by adding some constant value to the input block addresses. The defective blocks remaining even after applying the above two methods are repaired by using error control codes which correct soft errors induced by alpha particles in an on-line operation as well as hard errors induced by the remaining defective blocks. By using the proposed technique, this paper demonstrates a large capacity high-speed WSI file memory system implemented with high fabrication yield and low redundancy rate.

This paper proposes a new class of error locating codes which corrects random single-bit errors and indicates a location of an erroneous b-bit byte which includes e-bit errors, where 2 e b, called SECSe/bEL codes. This type of codes is very suitable for an application to memory systems constructed from byte-organized memory chips because this corrects random single-bit errors induced by soft-errors and also indicates the position of the faulty memory chips. This paper also gives a construction method of the proposed codes using tensor product of the two codes, i.e., the single b-bit byte error correcting codes and the single-bit error correcting and e-bit error detecting codes. This clarifies lower bounds and error control capabilities of the proposed codes.

Error locating codes were first presented in 1963 by J.K. Wolf and B.Elspas. Since then several code design methods have been proposed. However, their algebraic structure has not yet been clarified. It is apparent that necessary and sufficient conditions for error correcting/detecting codes can be expressed by Hamming distance, but, on the other hand, those for error locating codes cannot always be expressed only by Hamming distance. This paper presents necessary and sufficient conditions for error locating codes by using a newly defined metric and a function. The function represents the number of bytes where Hamming distance between corresponding bytes of two codewords has a certain integer range. These conditions show that an error locating code having special code parameters is an error correcting/detecting code. This concludes that error locating codes include existing bit/byte error correcting/detecting codes in their special cases.

This papter proposes a new type of unidirectional error control codes which indicates the location of unidirectional errors clustered in b-bit length, i.e., unidirectional byte error in b (b2) bits. Single unidirectional b-bit byte error locating codes, called SUbEL codes, are first clarified using necessary and sufficient conditions, and then code construction algorithm is demonstrated. The lower bound on check bit length of the SUbEL codes is derived. Based on this, the proposed codes are shown to be very efficient. Using the code design concept presented for the SUbEL codes, it is demonstrated that generalized unidirectional byte error locating codes are easily constructed.

Error correcting and/or detecting codes have been successfully used to improve the reliability of computer memories. To improve for error control in memory systems organized to have b bits per package, a new class of linear codes for simultaneous error correction and error detection is given. We refer to a group of b bits as a byte. This paper provides a new type of byte error detecting codes to correct single bit errors and detect single byte errors (SEC-SbED codes), and to correct single bit errors and detect double bit errors and single byte errors (SEC-DED-SbED codes). Form these codes, this paper demonstrates a new class of rotational SEC-SbED codes and rotational SEC-DED-SbED codes that are optimal for LSI construction of their encoding-decoding circuitries. The decoders for the proposed codes require very small amounts of extra circuitry over that required for SEC-DED (Single Error Correcting - Double Error Detecting) codes. The decoding speed is very high-equal to that of SEC-DED codes.

This paper proposes a unique type of signature testing for VLSIs, called referenceless signature testing. This testing automatically produces a reference value, i.e., correct signature, during its test intervals and compares it with compacted output of the circuit under test, i.e., signature. This makes testing much easier because it does not need the reference value, usually pre-calculated by simulation. This paper also proposes an extended form of this testing which offers economical and highly accurate one by using by-directional LFSRs for RAMs and sequential circuits. The proposed approach is successfully applied to these circuits, because the reference value can be automatically produced with their store operations and bi-directional input sequences for test data. An application of this testing to self-dual combinational circuits is also demonstrated in this paper.

One of the disadvantages of compressed data is their vulnerability, that is, even a single corrupted bit in compressed data may destroy the decompressed data completely. Therefore, Variable-to-Fixed length Arithmetic Coding, or VFAC, with error detecting capability is discussed. However, implementable error recovery method for compressed data has never been proposed. This paper proposes Burst Error Recovery Variable-to-Fixed length Arithmetic Coding, or BERVFAC, as well as Error Detecting Variable-to-Fixed length Arithmetic Coding, or EDVFAC. Both VFAC schemes achieve VF coding by inserting the internal states of the decompressor into compressed data. The internal states consist of width and offset of the sub-interval corresponding to the decompressed symbol and are also used for error detection. Convolutional operations are applied to encoding and decoding in order to propagate errors and improve error control capability. The proposed EDVFAC and BERVFAC are evaluated by theoretical analysis and computer simulations. The simulation results show that more than 99.99% of errors can be detected by EDVFAC. For BERVFAC, over 99.95% of l-burst errors can be corrected for l 32 and greater than 99.99% of other errors can be detected. The simulation results also show that the time-overhead necessary to decode the BERVFAC is about 12% when 10% of the received words are erroneous.

Since semiconductor memory chip has been growing rapidly in its capacity, memory testing has become a crucial problem in RAMs. This paper proposes a new RAM test algorithm, called generalized marching test (GMT), which detects static and dynamic pattern sensitive faults (PSF) in RAM chips. The memory array with N cells is partitioned into B sets in which every two cells has a cell-distance of at least d. The proposed GMT performs the ordinary marching test in each set and finally detects PSF having cell-distance d. By changing the number of partitions B, the GMT includes the ordinary marching test for B1 and the walking test for BN. This paper demonstrates the practical GMT with B2, capable of detecting PSF, as well as other faults, such as cell stuck-at faults, coupling faults, and decoder faults with a short testing time.

This paper proposes a new masking method for asymmetric line faults in LSIs using semi-distance codes, a class of non-linear codes. Faults caused by open or short circuit defects in line areas of LSIs can be made asymmetric by controlling the bus drive and the bus terminal gates. The conditions required for codes to mask these faults are clarified and the codes satisfying these conditions for random faults and adjacent faults, caused by line bridging defects, are constructed by using a new concept of semi-distance. This masking technique has the advantage that no additional circuits, such as error decoders, are needed. The codes have been applied to the bus lines in the address decoders of the 4-Mbit ROMs to improve fabrication yield of the LSIs.

M-spotty byte error control codes are very effective for correcting/detecting errors in semiconductor memory systems that employ recent high-density RAM chips with wide I/O data (e.g., 8, 16, or 32 bits). In this case, the width of the I/O data is one byte. A spotty byte error is defined as random t-bit errors within a byte of length b bits, where 1 ≤ t ≤ b. Then, an error is called an m-spotty byte error if at least one spotty byte error is present in a byte. M-spotty byte error control codes are characterized by the m-spotty distance, which includes the Hamming distance as a special case for t = 1 or t = b. The MacWilliams identity provides the relationship between the weight distribution of a code and that of its dual code. The present paper presents the MacWilliams identity for the m-spotty weight enumerator of m-spotty byte error control codes. In addition, the present paper clarifies that the indicated identity includes the MacWilliams identity for the Hamming weight enumerator as a special case.

Use of parity-based codes in computer systems can provide a cost-effective error detection and correction. Excellent parity-based main memory codes, such as odd-weight-column SEC-DED (Single bit Error Correcting Double bit Error Detecting) codes, can be used to arithmetic logic unit (ALU) by the technique proposed in this paper. They are more economical and better suited for a byte-sliced design of fault-tolerant computer systems than residue codes and triplication organization.