Single b-Bit Byte Error Correcting and Double Bit Error Detecting Codes for High-Speed Memory Systems

Eiji FUJIWARA, Mitsuru HAMADA

Summary :

This paper proposes new design methods for single b-bit (b2) byte error correcting and double bit error detecting code, called SbEC-DED code, suitable for high-speed memory systems using byte organized RAM chips. This new type of byte error control code is practical from the viewpoint of having less redundancy and stronger error control capability than the existing ones. A code design method using elements from a coset of subfield under addition gives the practical SbEC-DED code with 64 information bits and 4-bit byte length which has the same check-bit length, 12 bits, as that of the Hamming single byte error correcting code. This also has very high error detection capabilities of random double byte errors and of random triple bit errors.

• Publication: IEICE TRANSACTIONS on Fundamentals Vol.E76-A No.9 pp.1442-1448
• Publication Date: 1993/09/25
• Type of Manuscript: Special Section PAPER (Special Section on Information Theory and Its Applications)

Authors

Eiji FUJIWARA
Mitsuru HAMADA

Keyword

byte,  companion matrix,  subfield,  slimmed matrix,  coset,  SbEC-DED codes