IEICE TRANSACTIONS on transactions
Odd-Weight-Column b-Adjacent Error Correcting Codes
Summary :
The class of codes described in this paper is used for Single b-Adjacent bit-group Error Correction (SbEC). This is especially useful in large memory systems which use integrated semiconductor memory chips, each containing b-output bits. The proposed codes have odd-weight-column H-matrix characteristic and superior error detection capability, and facilitates the construction of modularized parallel high speed encoding / decoding network through rotational coding techniques. For a special case of b
- Publication
- IEICE TRANSACTIONS on transactions Vol.E61-E No.10 pp.781-787
- Publication Date
- 1978/10/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- PAPER
- Category
- Communication Theory
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Keyword
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Eiji FUJIWARA, "Odd-Weight-Column b-Adjacent Error Correcting Codes" in IEICE TRANSACTIONS on transactions,
vol. E61-E, no. 10, pp. 781-787, October 1978, doi: .
Abstract: The class of codes described in this paper is used for Single b-Adjacent bit-group Error Correction (SbEC). This is especially useful in large memory systems which use integrated semiconductor memory chips, each containing b-output bits. The proposed codes have odd-weight-column H-matrix characteristic and superior error detection capability, and facilitates the construction of modularized parallel high speed encoding / decoding network through rotational coding techniques. For a special case of b
URL: https://global.ieice.org/en_transactions/transactions/10.1587/e61-e_10_781/_p
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@ARTICLE{e61-e_10_781,
author={Eiji FUJIWARA, },
journal={IEICE TRANSACTIONS on transactions},
title={Odd-Weight-Column b-Adjacent Error Correcting Codes},
year={1978},
volume={E61-E},
number={10},
pages={781-787},
abstract={The class of codes described in this paper is used for Single b-Adjacent bit-group Error Correction (SbEC). This is especially useful in large memory systems which use integrated semiconductor memory chips, each containing b-output bits. The proposed codes have odd-weight-column H-matrix characteristic and superior error detection capability, and facilitates the construction of modularized parallel high speed encoding / decoding network through rotational coding techniques. For a special case of b
keywords={},
doi={},
ISSN={},
month={October},}
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TY - JOUR
TI - Odd-Weight-Column b-Adjacent Error Correcting Codes
T2 - IEICE TRANSACTIONS on transactions
SP - 781
EP - 787
AU - Eiji FUJIWARA
PY - 1978
DO -
JO - IEICE TRANSACTIONS on transactions
SN -
VL - E61-E
IS - 10
JA - IEICE TRANSACTIONS on transactions
Y1 - October 1978
AB - The class of codes described in this paper is used for Single b-Adjacent bit-group Error Correction (SbEC). This is especially useful in large memory systems which use integrated semiconductor memory chips, each containing b-output bits. The proposed codes have odd-weight-column H-matrix characteristic and superior error detection capability, and facilitates the construction of modularized parallel high speed encoding / decoding network through rotational coding techniques. For a special case of b
ER -
English
