Rotational Byte Error Detecting Codes for Memory Systems
Summary :
Error correcting and/or detecting codes have been successfully used to improve the reliability of computer memories. To improve for error control in memory systems organized to have b bits per package, a new class of linear codes for simultaneous error correction and error detection is given. We refer to a group of b bits as a byte. This paper provides a new type of byte error detecting codes to correct single bit errors and detect single byte errors (SEC-SbED codes), and to correct single bit errors and detect double bit errors and single byte errors (SEC-DED-SbED codes). Form these codes, this paper demonstrates a new class of rotational SEC-SbED codes and rotational SEC-DED-SbED codes that are optimal for LSI construction of their encoding-decoding circuitries. The decoders for the proposed codes require very small amounts of extra circuitry over that required for SEC-DED (Single Error Correcting - Double Error Detecting) codes. The decoding speed is very high-equal to that of SEC-DED codes.
- Publication
- IEICE TRANSACTIONS on transactions Vol.E64-E No.5 pp.342-349
- Publication Date
- 1981/05/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- PAPER
- Category
- Computers
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Eiji FUJIWARA, Shigeo KANEDA, "Rotational Byte Error Detecting Codes for Memory Systems" in IEICE TRANSACTIONS on transactions,
vol. E64-E, no. 5, pp. 342-349, May 1981, doi: .
Abstract: Error correcting and/or detecting codes have been successfully used to improve the reliability of computer memories. To improve for error control in memory systems organized to have b bits per package, a new class of linear codes for simultaneous error correction and error detection is given. We refer to a group of b bits as a byte. This paper provides a new type of byte error detecting codes to correct single bit errors and detect single byte errors (SEC-SbED codes), and to correct single bit errors and detect double bit errors and single byte errors (SEC-DED-SbED codes). Form these codes, this paper demonstrates a new class of rotational SEC-SbED codes and rotational SEC-DED-SbED codes that are optimal for LSI construction of their encoding-decoding circuitries. The decoders for the proposed codes require very small amounts of extra circuitry over that required for SEC-DED (Single Error Correcting - Double Error Detecting) codes. The decoding speed is very high-equal to that of SEC-DED codes.
URL: https://global.ieice.org/en_transactions/transactions/10.1587/e64-e_5_342/_p
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@ARTICLE{e64-e_5_342,
author={Eiji FUJIWARA, Shigeo KANEDA, },
journal={IEICE TRANSACTIONS on transactions},
title={Rotational Byte Error Detecting Codes for Memory Systems},
year={1981},
volume={E64-E},
number={5},
pages={342-349},
abstract={Error correcting and/or detecting codes have been successfully used to improve the reliability of computer memories. To improve for error control in memory systems organized to have b bits per package, a new class of linear codes for simultaneous error correction and error detection is given. We refer to a group of b bits as a byte. This paper provides a new type of byte error detecting codes to correct single bit errors and detect single byte errors (SEC-SbED codes), and to correct single bit errors and detect double bit errors and single byte errors (SEC-DED-SbED codes). Form these codes, this paper demonstrates a new class of rotational SEC-SbED codes and rotational SEC-DED-SbED codes that are optimal for LSI construction of their encoding-decoding circuitries. The decoders for the proposed codes require very small amounts of extra circuitry over that required for SEC-DED (Single Error Correcting - Double Error Detecting) codes. The decoding speed is very high-equal to that of SEC-DED codes.},
keywords={},
doi={},
ISSN={},
month={May},}
Copy
TY - JOUR
TI - Rotational Byte Error Detecting Codes for Memory Systems
T2 - IEICE TRANSACTIONS on transactions
SP - 342
EP - 349
AU - Eiji FUJIWARA
AU - Shigeo KANEDA
PY - 1981
DO -
JO - IEICE TRANSACTIONS on transactions
SN -
VL - E64-E
IS - 5
JA - IEICE TRANSACTIONS on transactions
Y1 - May 1981
AB - Error correcting and/or detecting codes have been successfully used to improve the reliability of computer memories. To improve for error control in memory systems organized to have b bits per package, a new class of linear codes for simultaneous error correction and error detection is given. We refer to a group of b bits as a byte. This paper provides a new type of byte error detecting codes to correct single bit errors and detect single byte errors (SEC-SbED codes), and to correct single bit errors and detect double bit errors and single byte errors (SEC-DED-SbED codes). Form these codes, this paper demonstrates a new class of rotational SEC-SbED codes and rotational SEC-DED-SbED codes that are optimal for LSI construction of their encoding-decoding circuitries. The decoders for the proposed codes require very small amounts of extra circuitry over that required for SEC-DED (Single Error Correcting - Double Error Detecting) codes. The decoding speed is very high-equal to that of SEC-DED codes.
ER -
English
