Adjacent Double Bit Error Correcting Codes with Single Byte Error Detecting Capability for Memory Systems

Ganesan UMANESAN; Eiji FUJIWARA

Adjacent Double Bit Error Correcting Codes with Single Byte Error Detecting Capability for Memory Systems

Ganesan UMANESAN, Eiji FUJIWARA

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Semiconductor memories are highly vulnerable to adjacent double bit errors for two reasons: 1) The bombardment of strong radioactive particles such as cosmic particles on DRAM chips and data bit lines. 2) The coupling noise in recent high density DRAM chips due to the wiring capacitance between two adjacent data bit lines. In addition, byte errors which result from entire chip failures are also a source of concern. Under this situation, codes capable of correcting adjacent double bit errors and simultaneously detecting single byte errors are suitable for application in semiconductor memory systems. This paper proposes two classes of codes called Adjacent Double bit Error Correcting-Single b-bit Byte Error Detecting (ADEC-S_bED) codes and Adjacent Double bit within a b-bit byte Error Correcting-Single b-bit byte Error Detecting ((ADEC)_b-S_bED) codes. For the practical case where byte length is 4 bits, the proposed codes require at most one extra check bit than their bounds. Furthermore, the number check bits required by the proposed (ADEC)₄-S₄ED code is same as that of the well known SEC-DED code for practical information bit lengths such as 64, 128, 256, etc.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E85-A No.2 pp.490-496

Publication Date: 2002/02/01

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Type of Manuscript: PAPER

Category: Coding Theory

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Ganesan UMANESAN, Eiji FUJIWARA, "Adjacent Double Bit Error Correcting Codes with Single Byte Error Detecting Capability for Memory Systems" in IEICE TRANSACTIONS on Fundamentals, vol. E85-A, no. 2, pp. 490-496, February 2002, doi: .
Abstract: Semiconductor memories are highly vulnerable to adjacent double bit errors for two reasons: 1) The bombardment of strong radioactive particles such as cosmic particles on DRAM chips and data bit lines. 2) The coupling noise in recent high density DRAM chips due to the wiring capacitance between two adjacent data bit lines. In addition, byte errors which result from entire chip failures are also a source of concern. Under this situation, codes capable of correcting adjacent double bit errors and simultaneously detecting single byte errors are suitable for application in semiconductor memory systems. This paper proposes two classes of codes called Adjacent Double bit Error Correcting-Single b-bit Byte Error Detecting (ADEC-S_bED) codes and Adjacent Double bit within a b-bit byte Error Correcting-Single b-bit byte Error Detecting ((ADEC)_b-S_bED) codes. For the practical case where byte length is 4 bits, the proposed codes require at most one extra check bit than their bounds. Furthermore, the number check bits required by the proposed (ADEC)₄-S₄ED code is same as that of the well known SEC-DED code for practical information bit lengths such as 64, 128, 256, etc.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e85-a_2_490/_p

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@ARTICLE{e85-a_2_490,
author={Ganesan UMANESAN, Eiji FUJIWARA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Adjacent Double Bit Error Correcting Codes with Single Byte Error Detecting Capability for Memory Systems},
year={2002},
volume={E85-A},
number={2},
pages={490-496},
abstract={Semiconductor memories are highly vulnerable to adjacent double bit errors for two reasons: 1) The bombardment of strong radioactive particles such as cosmic particles on DRAM chips and data bit lines. 2) The coupling noise in recent high density DRAM chips due to the wiring capacitance between two adjacent data bit lines. In addition, byte errors which result from entire chip failures are also a source of concern. Under this situation, codes capable of correcting adjacent double bit errors and simultaneously detecting single byte errors are suitable for application in semiconductor memory systems. This paper proposes two classes of codes called Adjacent Double bit Error Correcting-Single b-bit Byte Error Detecting (ADEC-S_bED) codes and Adjacent Double bit within a b-bit byte Error Correcting-Single b-bit byte Error Detecting ((ADEC)_b-S_bED) codes. For the practical case where byte length is 4 bits, the proposed codes require at most one extra check bit than their bounds. Furthermore, the number check bits required by the proposed (ADEC)₄-S₄ED code is same as that of the well known SEC-DED code for practical information bit lengths such as 64, 128, 256, etc.},
keywords={},
doi={},
ISSN={},
month={February},}

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TY - JOUR
TI - Adjacent Double Bit Error Correcting Codes with Single Byte Error Detecting Capability for Memory Systems
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 490
EP - 496
AU - Ganesan UMANESAN
AU - Eiji FUJIWARA
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E85-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2002
AB - Semiconductor memories are highly vulnerable to adjacent double bit errors for two reasons: 1) The bombardment of strong radioactive particles such as cosmic particles on DRAM chips and data bit lines. 2) The coupling noise in recent high density DRAM chips due to the wiring capacitance between two adjacent data bit lines. In addition, byte errors which result from entire chip failures are also a source of concern. Under this situation, codes capable of correcting adjacent double bit errors and simultaneously detecting single byte errors are suitable for application in semiconductor memory systems. This paper proposes two classes of codes called Adjacent Double bit Error Correcting-Single b-bit Byte Error Detecting (ADEC-S_bED) codes and Adjacent Double bit within a b-bit byte Error Correcting-Single b-bit byte Error Detecting ((ADEC)_b-S_bED) codes. For the practical case where byte length is 4 bits, the proposed codes require at most one extra check bit than their bounds. Furthermore, the number check bits required by the proposed (ADEC)₄-S₄ED code is same as that of the well known SEC-DED code for practical information bit lengths such as 64, 128, 256, etc.
ER -