IEICE TRANSACTIONS on Fundamentals
Random Double Bit Error Correcting--Single b-bit Byte Error Correcting (DEC-SbEC) Codes for Memory Systems
Summary :
Besides single byte errors which are caused by single chip failures, semiconductor memories used in some applications, such as satellite memory systems, are highly vulnerable to random double bit errors. It is therefore necessary to design Double bit Error Correcting--Single b-bit byte Error Correcting (DEC-SbEC) codes which correct both random double bit errors and single b-bit byte errors. This correspondence proposes a class of generic DEC-SbEC codes that are applicable to computer memory systems using recent high density DRAM chips with wide I/O data, such as, 8, 16 or 32 bits per chip. The proposed DEC-S8EC codes are suitable for memory systems using DRAM chips with 8-bit I/O data, and require 24 check bits for practical information lengths such as 64 and 128 bits.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E85-A No.1 pp.273-276
- Publication Date
- 2002/01/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- LETTER
- Category
- Coding Theory
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Ganesan UMANESAN, Eiji FUJIWARA, "Random Double Bit Error Correcting--Single b-bit Byte Error Correcting (DEC-SbEC) Codes for Memory Systems" in IEICE TRANSACTIONS on Fundamentals,
vol. E85-A, no. 1, pp. 273-276, January 2002, doi: .
Abstract: Besides single byte errors which are caused by single chip failures, semiconductor memories used in some applications, such as satellite memory systems, are highly vulnerable to random double bit errors. It is therefore necessary to design Double bit Error Correcting--Single b-bit byte Error Correcting (DEC-SbEC) codes which correct both random double bit errors and single b-bit byte errors. This correspondence proposes a class of generic DEC-SbEC codes that are applicable to computer memory systems using recent high density DRAM chips with wide I/O data, such as, 8, 16 or 32 bits per chip. The proposed DEC-S8EC codes are suitable for memory systems using DRAM chips with 8-bit I/O data, and require 24 check bits for practical information lengths such as 64 and 128 bits.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e85-a_1_273/_p
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@ARTICLE{e85-a_1_273,
author={Ganesan UMANESAN, Eiji FUJIWARA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Random Double Bit Error Correcting--Single b-bit Byte Error Correcting (DEC-SbEC) Codes for Memory Systems},
year={2002},
volume={E85-A},
number={1},
pages={273-276},
abstract={Besides single byte errors which are caused by single chip failures, semiconductor memories used in some applications, such as satellite memory systems, are highly vulnerable to random double bit errors. It is therefore necessary to design Double bit Error Correcting--Single b-bit byte Error Correcting (DEC-SbEC) codes which correct both random double bit errors and single b-bit byte errors. This correspondence proposes a class of generic DEC-SbEC codes that are applicable to computer memory systems using recent high density DRAM chips with wide I/O data, such as, 8, 16 or 32 bits per chip. The proposed DEC-S8EC codes are suitable for memory systems using DRAM chips with 8-bit I/O data, and require 24 check bits for practical information lengths such as 64 and 128 bits.},
keywords={},
doi={},
ISSN={},
month={January},}
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TY - JOUR
TI - Random Double Bit Error Correcting--Single b-bit Byte Error Correcting (DEC-SbEC) Codes for Memory Systems
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 273
EP - 276
AU - Ganesan UMANESAN
AU - Eiji FUJIWARA
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E85-A
IS - 1
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - January 2002
AB - Besides single byte errors which are caused by single chip failures, semiconductor memories used in some applications, such as satellite memory systems, are highly vulnerable to random double bit errors. It is therefore necessary to design Double bit Error Correcting--Single b-bit byte Error Correcting (DEC-SbEC) codes which correct both random double bit errors and single b-bit byte errors. This correspondence proposes a class of generic DEC-SbEC codes that are applicable to computer memory systems using recent high density DRAM chips with wide I/O data, such as, 8, 16 or 32 bits per chip. The proposed DEC-S8EC codes are suitable for memory systems using DRAM chips with 8-bit I/O data, and require 24 check bits for practical information lengths such as 64 and 128 bits.
ER -
English
