Single Byte Error Correcting Codes with Double Bit within a Block Error Correcting Capability for Memory Systems

Ganesan UMANESAN; Eiji FUJIWARA

Single Byte Error Correcting Codes with Double Bit within a Block Error Correcting Capability for Memory Systems

Ganesan UMANESAN, Eiji FUJIWARA

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Existing byte error control codes require too many check bits if applied to a memory system that uses recent semiconductor memory chips with wide I/O data such as 16 or 32 bits, i.e., b=16 or 32. On the other hand, semiconductor memory chips are highly vulnerable to random double bit within a memory chip errors when they are used in some applications, such as satellite memory systems. Under this situation, it becomes necessary to design suitable new codes with double bit within a chip error correcting capability for computer memory systems. This correspondence proposes a class of codes called Double bit within a block Error Correcting - Single b-bit byte Error Correcting ((DEC)_B-S_bEC) codes where block and byte correspond to memory chip and memory sub-array data outputs, respectively. The proposed codes provide protection from both random double bit errors and single sub-array data faults. For most of the practical cases, the (DEC)_B-S_bEC codes presented in this correspondence have the capability of accommodating the check bits in a single dedicated memory chip.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E85-A No.2 pp.513-517

Publication Date: 2002/02/01

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Type of Manuscript: LETTER

Category: Coding Theory

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Ganesan UMANESAN, Eiji FUJIWARA, "Single Byte Error Correcting Codes with Double Bit within a Block Error Correcting Capability for Memory Systems" in IEICE TRANSACTIONS on Fundamentals, vol. E85-A, no. 2, pp. 513-517, February 2002, doi: .
Abstract: Existing byte error control codes require too many check bits if applied to a memory system that uses recent semiconductor memory chips with wide I/O data such as 16 or 32 bits, i.e., b=16 or 32. On the other hand, semiconductor memory chips are highly vulnerable to random double bit within a memory chip errors when they are used in some applications, such as satellite memory systems. Under this situation, it becomes necessary to design suitable new codes with double bit within a chip error correcting capability for computer memory systems. This correspondence proposes a class of codes called Double bit within a block Error Correcting - Single b-bit byte Error Correcting ((DEC)_B-S_bEC) codes where block and byte correspond to memory chip and memory sub-array data outputs, respectively. The proposed codes provide protection from both random double bit errors and single sub-array data faults. For most of the practical cases, the (DEC)_B-S_bEC codes presented in this correspondence have the capability of accommodating the check bits in a single dedicated memory chip.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e85-a_2_513/_p

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@ARTICLE{e85-a_2_513,
author={Ganesan UMANESAN, Eiji FUJIWARA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Single Byte Error Correcting Codes with Double Bit within a Block Error Correcting Capability for Memory Systems},
year={2002},
volume={E85-A},
number={2},
pages={513-517},
abstract={Existing byte error control codes require too many check bits if applied to a memory system that uses recent semiconductor memory chips with wide I/O data such as 16 or 32 bits, i.e., b=16 or 32. On the other hand, semiconductor memory chips are highly vulnerable to random double bit within a memory chip errors when they are used in some applications, such as satellite memory systems. Under this situation, it becomes necessary to design suitable new codes with double bit within a chip error correcting capability for computer memory systems. This correspondence proposes a class of codes called Double bit within a block Error Correcting - Single b-bit byte Error Correcting ((DEC)_B-S_bEC) codes where block and byte correspond to memory chip and memory sub-array data outputs, respectively. The proposed codes provide protection from both random double bit errors and single sub-array data faults. For most of the practical cases, the (DEC)_B-S_bEC codes presented in this correspondence have the capability of accommodating the check bits in a single dedicated memory chip.},
keywords={},
doi={},
ISSN={},
month={February},}

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TY - JOUR
TI - Single Byte Error Correcting Codes with Double Bit within a Block Error Correcting Capability for Memory Systems
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 513
EP - 517
AU - Ganesan UMANESAN
AU - Eiji FUJIWARA
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E85-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2002
AB - Existing byte error control codes require too many check bits if applied to a memory system that uses recent semiconductor memory chips with wide I/O data such as 16 or 32 bits, i.e., b=16 or 32. On the other hand, semiconductor memory chips are highly vulnerable to random double bit within a memory chip errors when they are used in some applications, such as satellite memory systems. Under this situation, it becomes necessary to design suitable new codes with double bit within a chip error correcting capability for computer memory systems. This correspondence proposes a class of codes called Double bit within a block Error Correcting - Single b-bit byte Error Correcting ((DEC)_B-S_bEC) codes where block and byte correspond to memory chip and memory sub-array data outputs, respectively. The proposed codes provide protection from both random double bit errors and single sub-array data faults. For most of the practical cases, the (DEC)_B-S_bEC codes presented in this correspondence have the capability of accommodating the check bits in a single dedicated memory chip.
ER -