An On-Chip Power-on Reset Circuit for Low Voltage Technology

Takeo YASUDA; Masaaki YAMAMOTO

An On-Chip Power-on Reset Circuit for Low Voltage Technology

Takeo YASUDA, Masaaki YAMAMOTO

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The power supply voltage of LSI has been lowered due to system requirements for low power dissipation. An on-chip power-on reset pulse generator (POR-PG) is used to determine the initial state of the memory devices of the system LSI. The requirement for the POR-PG is strict for lower power supply voltage because noise margin is smaller relatively. This paper describes a POR-PG for low power voltage supply (V_dd) which overcomes these problems. Hardware measurement proves improved pulse height relative to various power-on profiles (slope, rise time etc.) and fluctuations of temperature and process. Further, the design provides robust noise immunity against voltage fluctuations on the power supply line. The circuit is implemented within a small area (115 µm 345 µm) in the input/output buffer area of a micro-processor and hard-disk controller integrated LSI with 0.25-µm four-layer-metal CMOS technology.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E85-A No.2 pp.366-372

Publication Date: 2002/02/01

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Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)

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Takeo YASUDA, Masaaki YAMAMOTO, "An On-Chip Power-on Reset Circuit for Low Voltage Technology" in IEICE TRANSACTIONS on Fundamentals, vol. E85-A, no. 2, pp. 366-372, February 2002, doi: .
Abstract: The power supply voltage of LSI has been lowered due to system requirements for low power dissipation. An on-chip power-on reset pulse generator (POR-PG) is used to determine the initial state of the memory devices of the system LSI. The requirement for the POR-PG is strict for lower power supply voltage because noise margin is smaller relatively. This paper describes a POR-PG for low power voltage supply (V_dd) which overcomes these problems. Hardware measurement proves improved pulse height relative to various power-on profiles (slope, rise time etc.) and fluctuations of temperature and process. Further, the design provides robust noise immunity against voltage fluctuations on the power supply line. The circuit is implemented within a small area (115 µm 345 µm) in the input/output buffer area of a micro-processor and hard-disk controller integrated LSI with 0.25-µm four-layer-metal CMOS technology.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e85-a_2_366/_p

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@ARTICLE{e85-a_2_366,
author={Takeo YASUDA, Masaaki YAMAMOTO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={An On-Chip Power-on Reset Circuit for Low Voltage Technology},
year={2002},
volume={E85-A},
number={2},
pages={366-372},
abstract={The power supply voltage of LSI has been lowered due to system requirements for low power dissipation. An on-chip power-on reset pulse generator (POR-PG) is used to determine the initial state of the memory devices of the system LSI. The requirement for the POR-PG is strict for lower power supply voltage because noise margin is smaller relatively. This paper describes a POR-PG for low power voltage supply (V_dd) which overcomes these problems. Hardware measurement proves improved pulse height relative to various power-on profiles (slope, rise time etc.) and fluctuations of temperature and process. Further, the design provides robust noise immunity against voltage fluctuations on the power supply line. The circuit is implemented within a small area (115 µm 345 µm) in the input/output buffer area of a micro-processor and hard-disk controller integrated LSI with 0.25-µm four-layer-metal CMOS technology.},
keywords={},
doi={},
ISSN={},
month={February},}

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TY - JOUR
TI - An On-Chip Power-on Reset Circuit for Low Voltage Technology
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 366
EP - 372
AU - Takeo YASUDA
AU - Masaaki YAMAMOTO
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E85-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2002
AB - The power supply voltage of LSI has been lowered due to system requirements for low power dissipation. An on-chip power-on reset pulse generator (POR-PG) is used to determine the initial state of the memory devices of the system LSI. The requirement for the POR-PG is strict for lower power supply voltage because noise margin is smaller relatively. This paper describes a POR-PG for low power voltage supply (V_dd) which overcomes these problems. Hardware measurement proves improved pulse height relative to various power-on profiles (slope, rise time etc.) and fluctuations of temperature and process. Further, the design provides robust noise immunity against voltage fluctuations on the power supply line. The circuit is implemented within a small area (115 µm 345 µm) in the input/output buffer area of a micro-processor and hard-disk controller integrated LSI with 0.25-µm four-layer-metal CMOS technology.
ER -