Variable VCC Design Techniques for Battery-Operated DRAM's
Summary :
Wide-voltage-range DRAM's with extended data retention are desirable for battery-operated or portable computers and consumer devices. This paper describes the techniques required to obtain wide operation, functionality, and performance of standard DRAM's from 1.8 V (2 NiCd or Alkaline batteries) to 3.6 V (upper end of LVTTL standard). Specific techniques shown are: 1) a low-power and low-voltage reference generator for detecting VCC level; 2) compensation of dc generators, VBB and VPP, for obtaining high speed at reduced voltages; 3) a static word-line driver and latch-isolation sense amplifier for reducing operating current; and 4) a programmable VCC variable self-refresh scheme for obtaining maximum data retention time over a full operating range. A sub-50-ns access time is obtained for a 16M DRAM(2M
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E76-C No.5 pp.839-843
- Publication Date
- 1993/05/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section on the 1992 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.28, No.4 April 1993))
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Seung-Moon YOO, Ejaz HAQ, Seung-Hoon LEE, Yun-Ho CHOI, Soo-IN CHO, Nam-Soo KANG, Daeje CHIN, "Variable VCC Design Techniques for Battery-Operated DRAM's" in IEICE TRANSACTIONS on Electronics,
vol. E76-C, no. 5, pp. 839-843, May 1993, doi: .
Abstract: Wide-voltage-range DRAM's with extended data retention are desirable for battery-operated or portable computers and consumer devices. This paper describes the techniques required to obtain wide operation, functionality, and performance of standard DRAM's from 1.8 V (2 NiCd or Alkaline batteries) to 3.6 V (upper end of LVTTL standard). Specific techniques shown are: 1) a low-power and low-voltage reference generator for detecting VCC level; 2) compensation of dc generators, VBB and VPP, for obtaining high speed at reduced voltages; 3) a static word-line driver and latch-isolation sense amplifier for reducing operating current; and 4) a programmable VCC variable self-refresh scheme for obtaining maximum data retention time over a full operating range. A sub-50-ns access time is obtained for a 16M DRAM(2M
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e76-c_5_839/_p
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@ARTICLE{e76-c_5_839,
author={Seung-Moon YOO, Ejaz HAQ, Seung-Hoon LEE, Yun-Ho CHOI, Soo-IN CHO, Nam-Soo KANG, Daeje CHIN, },
journal={IEICE TRANSACTIONS on Electronics},
title={Variable VCC Design Techniques for Battery-Operated DRAM's},
year={1993},
volume={E76-C},
number={5},
pages={839-843},
abstract={Wide-voltage-range DRAM's with extended data retention are desirable for battery-operated or portable computers and consumer devices. This paper describes the techniques required to obtain wide operation, functionality, and performance of standard DRAM's from 1.8 V (2 NiCd or Alkaline batteries) to 3.6 V (upper end of LVTTL standard). Specific techniques shown are: 1) a low-power and low-voltage reference generator for detecting VCC level; 2) compensation of dc generators, VBB and VPP, for obtaining high speed at reduced voltages; 3) a static word-line driver and latch-isolation sense amplifier for reducing operating current; and 4) a programmable VCC variable self-refresh scheme for obtaining maximum data retention time over a full operating range. A sub-50-ns access time is obtained for a 16M DRAM(2M
keywords={},
doi={},
ISSN={},
month={May},}
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TY - JOUR
TI - Variable VCC Design Techniques for Battery-Operated DRAM's
T2 - IEICE TRANSACTIONS on Electronics
SP - 839
EP - 843
AU - Seung-Moon YOO
AU - Ejaz HAQ
AU - Seung-Hoon LEE
AU - Yun-Ho CHOI
AU - Soo-IN CHO
AU - Nam-Soo KANG
AU - Daeje CHIN
PY - 1993
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E76-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 1993
AB - Wide-voltage-range DRAM's with extended data retention are desirable for battery-operated or portable computers and consumer devices. This paper describes the techniques required to obtain wide operation, functionality, and performance of standard DRAM's from 1.8 V (2 NiCd or Alkaline batteries) to 3.6 V (upper end of LVTTL standard). Specific techniques shown are: 1) a low-power and low-voltage reference generator for detecting VCC level; 2) compensation of dc generators, VBB and VPP, for obtaining high speed at reduced voltages; 3) a static word-line driver and latch-isolation sense amplifier for reducing operating current; and 4) a programmable VCC variable self-refresh scheme for obtaining maximum data retention time over a full operating range. A sub-50-ns access time is obtained for a 16M DRAM(2M
ER -
English
