IEICE TRANSACTIONS on Electronics
16-Mb Synchronous DRAM with 125-Mbyte/s Data Rate
Summary :
In order to keep up with the growing need for memory bandwidth at low cost, a new synchronous DRAM (SDRAM) architecture is proposed. The SDRAM has programmable latency, burst length, and burst type for wide variety of applications. The experimental 16M SDRAM (2M
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E77-C No.5 pp.859-863
- Publication Date
- 1994/05/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section LETTER (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))
- Category
Authors
Yunho CHOI
Myungho KIM
Hyunsoon JANG
Taejin KIM
Seung-hoon LEE
Ho-cheol LEE，Churoo PARK
Siyeol LEE
Cheol-soo KIM
Sooin CHO
Ejaz HAQ
Joel KARP
Daeje CHIN
Keyword
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Yunho CHOI, Myungho KIM, Hyunsoon JANG, Taejin KIM, Seung-hoon LEE, Ho-cheol LEE,Churoo PARK, Siyeol LEE, Cheol-soo KIM, Sooin CHO, Ejaz HAQ, Joel KARP, Daeje CHIN, "16-Mb Synchronous DRAM with 125-Mbyte/s Data Rate" in IEICE TRANSACTIONS on Electronics,
vol. E77-C, no. 5, pp. 859-863, May 1994, doi: .
Abstract: In order to keep up with the growing need for memory bandwidth at low cost, a new synchronous DRAM (SDRAM) architecture is proposed. The SDRAM has programmable latency, burst length, and burst type for wide variety of applications. The experimental 16M SDRAM (2M
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e77-c_5_859/_p
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@ARTICLE{e77-c_5_859,
author={Yunho CHOI, Myungho KIM, Hyunsoon JANG, Taejin KIM, Seung-hoon LEE, Ho-cheol LEE,Churoo PARK, Siyeol LEE, Cheol-soo KIM, Sooin CHO, Ejaz HAQ, Joel KARP, Daeje CHIN, },
journal={IEICE TRANSACTIONS on Electronics},
title={16-Mb Synchronous DRAM with 125-Mbyte/s Data Rate},
year={1994},
volume={E77-C},
number={5},
pages={859-863},
abstract={In order to keep up with the growing need for memory bandwidth at low cost, a new synchronous DRAM (SDRAM) architecture is proposed. The SDRAM has programmable latency, burst length, and burst type for wide variety of applications. The experimental 16M SDRAM (2M
keywords={},
doi={},
ISSN={},
month={May},}
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TY - JOUR
TI - 16-Mb Synchronous DRAM with 125-Mbyte/s Data Rate
T2 - IEICE TRANSACTIONS on Electronics
SP - 859
EP - 863
AU - Yunho CHOI
AU - Myungho KIM
AU - Hyunsoon JANG
AU - Taejin KIM
AU - Seung-hoon LEE
AU - Ho-cheol LEE,Churoo PARK
AU - Siyeol LEE
AU - Cheol-soo KIM
AU - Sooin CHO
AU - Ejaz HAQ
AU - Joel KARP
AU - Daeje CHIN
PY - 1994
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E77-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 1994
AB - In order to keep up with the growing need for memory bandwidth at low cost, a new synchronous DRAM (SDRAM) architecture is proposed. The SDRAM has programmable latency, burst length, and burst type for wide variety of applications. The experimental 16M SDRAM (2M
ER -
English
