An 8.5-ns 112-b Transmission Gate Adder with a Conflict-Free Bypass Circuit

T. SATO; M. SAKATE; H. OKADA; T. SUKEMURA; G. GOTO

An 8.5-ns 112-b Transmission Gate Adder with a Conflict-Free Bypass Circuit

T. SATO, M. SAKATE, H. OKADA, T. SUKEMURA, G. GOTO

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In this paper, we discuss the weak point of a conventional bypass circuit, or carry-skip paths in a Manchester adder, and propose a new bypass circuit and its control scheme to avoid transitory fighting that causes an intermediate voltage. A 112-b transmission gate adder is presented, which uses a group of three mutually exclusive transmission gates for the carry-skip paths and a new conditional sum generation circuit. It has an estimated propagation delay time of 8.5 ns and 6941 transistors, both of which are smaller than those of conventional carry select adders. The adder is integrated into an area of 0.41 3.36 mm² achieved by a 0.8-µm, triple-metal, full-CMOS process.

Publication: IEICE TRANSACTIONS on Electronics Vol.E75-C No.4 pp.555-557

Publication Date: 1992/04/25

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Type of Manuscript: Special Section LETTER (Joint Special Issue on the 1991 VLSI Circuits Symposium)

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T. SATO
M. SAKATE
H. OKADA
T. SUKEMURA
G. GOTO

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T. SATO, M. SAKATE, H. OKADA, T. SUKEMURA, G. GOTO, "An 8.5-ns 112-b Transmission Gate Adder with a Conflict-Free Bypass Circuit" in IEICE TRANSACTIONS on Electronics, vol. E75-C, no. 4, pp. 555-557, April 1992, doi: .
Abstract: In this paper, we discuss the weak point of a conventional bypass circuit, or carry-skip paths in a Manchester adder, and propose a new bypass circuit and its control scheme to avoid transitory fighting that causes an intermediate voltage. A 112-b transmission gate adder is presented, which uses a group of three mutually exclusive transmission gates for the carry-skip paths and a new conditional sum generation circuit. It has an estimated propagation delay time of 8.5 ns and 6941 transistors, both of which are smaller than those of conventional carry select adders. The adder is integrated into an area of 0.41 3.36 mm² achieved by a 0.8-µm, triple-metal, full-CMOS process.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e75-c_4_555/_p

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@ARTICLE{e75-c_4_555,
author={T. SATO, M. SAKATE, H. OKADA, T. SUKEMURA, G. GOTO, },
journal={IEICE TRANSACTIONS on Electronics},
title={An 8.5-ns 112-b Transmission Gate Adder with a Conflict-Free Bypass Circuit},
year={1992},
volume={E75-C},
number={4},
pages={555-557},
abstract={In this paper, we discuss the weak point of a conventional bypass circuit, or carry-skip paths in a Manchester adder, and propose a new bypass circuit and its control scheme to avoid transitory fighting that causes an intermediate voltage. A 112-b transmission gate adder is presented, which uses a group of three mutually exclusive transmission gates for the carry-skip paths and a new conditional sum generation circuit. It has an estimated propagation delay time of 8.5 ns and 6941 transistors, both of which are smaller than those of conventional carry select adders. The adder is integrated into an area of 0.41 3.36 mm² achieved by a 0.8-µm, triple-metal, full-CMOS process.},
keywords={},
doi={},
ISSN={},
month={April},}

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TY - JOUR
TI - An 8.5-ns 112-b Transmission Gate Adder with a Conflict-Free Bypass Circuit
T2 - IEICE TRANSACTIONS on Electronics
SP - 555
EP - 557
AU - T. SATO
AU - M. SAKATE
AU - H. OKADA
AU - T. SUKEMURA
AU - G. GOTO
PY - 1992
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E75-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 1992
AB - In this paper, we discuss the weak point of a conventional bypass circuit, or carry-skip paths in a Manchester adder, and propose a new bypass circuit and its control scheme to avoid transitory fighting that causes an intermediate voltage. A 112-b transmission gate adder is presented, which uses a group of three mutually exclusive transmission gates for the carry-skip paths and a new conditional sum generation circuit. It has an estimated propagation delay time of 8.5 ns and 6941 transistors, both of which are smaller than those of conventional carry select adders. The adder is integrated into an area of 0.41 3.36 mm² achieved by a 0.8-µm, triple-metal, full-CMOS process.
ER -