IEICE TRANSACTIONS on Electronics
A High-Speed Sensing Scheme for 1T Dynamic RAM's Utilizing the Clamped Bit-Line Sense Amplifier
Summary :
A clamped-bit-line sense amplifier (CBLSA) capable of very high-speed operation in one-transistor (1T) DRAM applications has been developed. Results from an experimental test chip demonstrate that the speed of the new circuit is insensitive to bit-line capacitance. Circuit speed is also found to be insensitive to initial bit-line difference voltage. The CBLSA maintains a low-impedance fixed potential on the bit lines during sensing, virtually eliminating sensitivity to inter-bit-line noise coupling and minimizing power supply bounce during sensing. The new sense amplifier operates at higher speeds than conventional circuits and still dissipates less power.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E75-C No.4 pp.516-523
- Publication Date
- 1992/04/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Joint Special Issue on the 1991 VLSI Circuits Symposium)
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Travis N. BLALOCK, Richard C. JAEGER, "A High-Speed Sensing Scheme for 1T Dynamic RAM's Utilizing the Clamped Bit-Line Sense Amplifier" in IEICE TRANSACTIONS on Electronics,
vol. E75-C, no. 4, pp. 516-523, April 1992, doi: .
Abstract: A clamped-bit-line sense amplifier (CBLSA) capable of very high-speed operation in one-transistor (1T) DRAM applications has been developed. Results from an experimental test chip demonstrate that the speed of the new circuit is insensitive to bit-line capacitance. Circuit speed is also found to be insensitive to initial bit-line difference voltage. The CBLSA maintains a low-impedance fixed potential on the bit lines during sensing, virtually eliminating sensitivity to inter-bit-line noise coupling and minimizing power supply bounce during sensing. The new sense amplifier operates at higher speeds than conventional circuits and still dissipates less power.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e75-c_4_516/_p
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@ARTICLE{e75-c_4_516,
author={Travis N. BLALOCK, Richard C. JAEGER, },
journal={IEICE TRANSACTIONS on Electronics},
title={A High-Speed Sensing Scheme for 1T Dynamic RAM's Utilizing the Clamped Bit-Line Sense Amplifier},
year={1992},
volume={E75-C},
number={4},
pages={516-523},
abstract={A clamped-bit-line sense amplifier (CBLSA) capable of very high-speed operation in one-transistor (1T) DRAM applications has been developed. Results from an experimental test chip demonstrate that the speed of the new circuit is insensitive to bit-line capacitance. Circuit speed is also found to be insensitive to initial bit-line difference voltage. The CBLSA maintains a low-impedance fixed potential on the bit lines during sensing, virtually eliminating sensitivity to inter-bit-line noise coupling and minimizing power supply bounce during sensing. The new sense amplifier operates at higher speeds than conventional circuits and still dissipates less power.},
keywords={},
doi={},
ISSN={},
month={April},}
Copy
TY - JOUR
TI - A High-Speed Sensing Scheme for 1T Dynamic RAM's Utilizing the Clamped Bit-Line Sense Amplifier
T2 - IEICE TRANSACTIONS on Electronics
SP - 516
EP - 523
AU - Travis N. BLALOCK
AU - Richard C. JAEGER
PY - 1992
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E75-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 1992
AB - A clamped-bit-line sense amplifier (CBLSA) capable of very high-speed operation in one-transistor (1T) DRAM applications has been developed. Results from an experimental test chip demonstrate that the speed of the new circuit is insensitive to bit-line capacitance. Circuit speed is also found to be insensitive to initial bit-line difference voltage. The CBLSA maintains a low-impedance fixed potential on the bit lines during sensing, virtually eliminating sensitivity to inter-bit-line noise coupling and minimizing power supply bounce during sensing. The new sense amplifier operates at higher speeds than conventional circuits and still dissipates less power.
ER -
English
