An on-chip SIDO DC-DC boost converter core that can be used for both battery and solar cell operating applications is proposed. The converter is able to supply a current of up to around 30mA with an on-chip driver and more than 100mA by using an off-chip power MOS driver. The cross regulation problem was solved by inserting an extra cycle. Efficiencies of 85% and 84% were achieved for each driving mode. Complicated maximum power point tracking (MPPT) controls are available for a solar cell operation. An embedded micro-computer can be used to calculate a complicated algorithm. The converter exploits 99% of the expected maximum power of the solar cell. The converter protects the leak current that flows through the solar cell when there is no light. The proposed protection circuits reduce the leak current by three orders of magnitude without any performance loss.

We developed Millimeter-wave high speed spot communication system using radio-over-fiber technology for ITS telecommunication use. This system has wide bandwidth and provides a high-capacity channel between the base station and parked vehicles. The installation conditions (height, elevation angle) of the base station antenna of this system that enabled the largest possible communication area were obtained by simulation. In addition, we measured propagation and transmission characteristics. The width of the error-free service area was 8 m, which enables three vehicles to be served in one service area.

Various low power technologies have been developed and applied to LSIs from the point of device and circuit design. A lot more CPU cores as well as function IPs are integrated on a single chip LSI today. Therefore, not only the device and circuit low power technologies, but software power control technologies are becoming more important to reduce active power of application systems. This paper overviews the low power technologies and defines power management platform as a combination of hardware functions and software programming interface. This paper discusses importance of the power management platform and direction of its development.

Improving energy efficiency is critical for embedded systems in our rapidly evolving information society. Near real-time data processing tasks, such as multimedia streaming applications, exhibit a common fact that their deadline periods are longer than their input intervals due to buffering. In general, executing tasks at lower performance is more energy efficient. On the other hand, higher performance is necessary for huge tasks to meet their deadlines. To minimize the energy consumption while meeting deadlines strictly, adaptive task scheduling including dynamic performance mode selection is very important. In this work, we propose an energy efficient slack-based task scheduling algorithm for such tasks by adapting to task size variations and applying DVFS with the help of statistical analysis. We confirmed that our proposal can further reduce the energy consumption when compared to oracle frame-based scheduling.

This paper describes a top-down design methodology to optimize resonant capacitance in a wireless power transfer system with 3-D stacked two receivers. A 1:2 selective wireless power transfer is realized by a frequency/time division multiplexing scheme. The power transfer function is analytically formulated and the optimum tuning capacitance is derived, which is validated by comparing with system simulation results. By using the optimized values, power transfer efficiencies at 6.78MHz and 13.56MHz are simulated to be 80% and 84%, respectively, which are <3% worse than a conventional wireless power transfer system.

This paper propeses advanced multi-stage interference canceller systems (MSICS) wihch can estimate radio channels with precision in the direct sequence code division multiple access (DS-CDMA) systems. For the accurate channel estimations, we propose a novel radio channel estimation method specified by the following two signal processing methods. One is the radio channel estimation using both pilot and information signals. The other is the correction of estimated radio channels using adaptation algorithm based on the least mean square method (LMS). The results of our computer simulation indicate that the cell capacity of the advanced MSICS in serial and parallel structure can be increased by about 1.8 and 1.3 times over that of a receiver which does not has a canceller, respectively. Moreover, the advanced MSICS in serial and parallel structure can reduce the required Eb/No by about 1.2 dB and 1.6 dB at a BER of 10-3 compared to the Eb/No of a basic MSICS, respectively.

Many embedded system application in ubiquitous network strongly require the high performance SoC with overcoming the physical limitations in the advanced CMOS. To develop these SoC, the continuous design efforts have been done. The initial efforts are the primitive level circuit technique and power switching control method for suppressing the standby currents. However, the additional physical limitations and system enhancements becomes main factors, the new design efforts have been proposed. These design efforts are the application-oriented technologies from the system level to device level. This paper introduces the self voltage controlled technique to cancel the PVT (process, voltage, and temperature) variation, power distribution and power management for cellular phone application, parallel algorithm and optimized layout DSP, and massively parallel fine-grained SIMD processor for next multimedia application. The high performance SoC for the embedded are achieved by providing the components of the system level IPs and making the application oriented SoC platform.

This paper describes the design and evaluation of a massively parallel processor base on Matrix architecture which is suitable for portable multimedia applications. The proposed architecture in this paper achieves 40 GOPS of 16-bit fixed-point additions at 200 MHz clock frequency and 250 mW power dissipation. In addition, 1 M-bit SRAM for data registers and 2,048 2-bit processing elements connected by a flexible switching network are integrated in 3.1 mm2 in 90 nm low-power CMOS technology. The energy-efficient Matrix architecture supports 2,048-way parallel operations and the programmable functions required for multimedia SoCs.

We have developed an IP-over-Ethernet-based ultra high-speed multimedia wireless LAN prototype operating in the 60-GHz band. It employs a media-access-control (MAC) protocol based on reservation-based slotted idle signal multiple access (RS-ISMA), which was implemented in the former prototype, for supporting various IP traffic such as real-time AV traffic and best-effort web traffic. The protocol also has a new function called NACK sensing for the efficient retransmission of wireless multicast packets. It was demonstrated that the prototype can provide the world's fastest radio transmission speed of 128 Mbps for two-way communications. We have measured the throughput and latency of the prototype LAN for Ethernet-frame transmission in a point-to-point baseband-connected environment. The measurement showed that the prototype LAN provides a maximum throughput of 30 Mbps, and that the measured throughput agrees with the theoretically predicted throughput. It also showed that the maximum latency, which includes switching and routing latency in the wired part, is below 1 msec.

This letter presents a new design method for approximate inverse systems using all-pass networks. The efficacy of approximate inverse systems for input and parameter estimation of nonminimum phase systems is well recognized. in the previous methods, only time domain design of FIR (finite impulse response) type approximate inverse systems were considered. Here, we demonstrate that IIR (infinite impulse response) type approximate inverse systems outperform the previous methods. A nonlinear optimization technique is adopted for designing the proposed system in the frequency domain. Numerical examples are also presented to show the effectiveness of the proposed method.

A low-power microcontroller has been developed with 0.10 µm bulk compatible body-tied SOI technology. For this work, only two new masks are required. For the other layers, existing masks of a prior work developed with 0.18 µm bulk CMOS technology can be applied without any changes. With the SOI technology, the high-speed operation of over 600 MHz has been achieved at a supply voltage of 1.2 V, which is 1.5 times faster than prior work. Also, a five times improvement in the power-delay product has been achieved at a supply voltage 0.8 V. Moreover, the compatibility of the SOI technology with bulk CMOS has been verified, because all circuit blocks of the chip, including logic, memory, analog circuit, and PLL, are completely functional, even though only two new masks are used.