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Yasunobu NAKASE Yasuhiro IDO Tsukasa OISHI Toru SHIMIZU
An on-chip SIDO DC-DC boost converter core that can be used for both battery and solar cell operating applications is proposed. The converter is able to supply a current of up to around 30mA with an on-chip driver and more than 100mA by using an off-chip power MOS driver. The cross regulation problem was solved by inserting an extra cycle. Efficiencies of 85% and 84% were achieved for each driving mode. Complicated maximum power point tracking (MPPT) controls are available for a solar cell operation. An embedded micro-computer can be used to calculate a complicated algorithm. The converter exploits 99% of the expected maximum power of the solar cell. The converter protects the leak current that flows through the solar cell when there is no light. The proposed protection circuits reduce the leak current by three orders of magnitude without any performance loss.
Masaki TSUKUDE Tsukasa OISHI Kazutami ARIMOTO Hideto HIDAKA Kazuyasu FUJISHIMA
An improved array architecture to realize fast access, low power dissipation, and wide operating margin, for the 16 Mbit DRAM is proposed. A high speed access is obtained by the fully embedded sense drive scheme for the RAS access time (tRAC), and the special page mode with the hierarchical I/O data bus lines and multi-purpose-register (MPR) for the column address access time (tCAA). A low power dissipation and wide operating margin are obtained by the improved twisted-bit-line (TBL) architecture with double dummy canceling. The 16 Mb DRAM using these architectures has 38 ns tRAC, 14 ns tCAA and 75 mA power dissipation at the typical condition.