A New Array Architecture for 16 Mb DRAMs with Special Page Mode
Summary :
An improved array architecture to realize fast access, low power dissipation, and wide operating margin, for the 16 Mbit DRAM is proposed. A high speed access is obtained by the fully embedded sense drive scheme for the RAS access time (tRAC), and the special page mode with the hierarchical I/O data bus lines and multi-purpose-register (MPR) for the column address access time (tCAA). A low power dissipation and wide operating margin are obtained by the improved twisted-bit-line (TBL) architecture with double dummy canceling. The 16 Mb DRAM using these architectures has 38 ns tRAC, 14 ns tCAA and 75 mA power dissipation at the typical condition.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E75-C No.10 pp.1267-1274
- Publication Date
- 1992/10/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- PAPER
- Category
- Integrated Electronics
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Masaki TSUKUDE, Tsukasa OISHI, Kazutami ARIMOTO, Hideto HIDAKA, Kazuyasu FUJISHIMA, "A New Array Architecture for 16 Mb DRAMs with Special Page Mode" in IEICE TRANSACTIONS on Electronics,
vol. E75-C, no. 10, pp. 1267-1274, October 1992, doi: .
Abstract: An improved array architecture to realize fast access, low power dissipation, and wide operating margin, for the 16 Mbit DRAM is proposed. A high speed access is obtained by the fully embedded sense drive scheme for the RAS access time (tRAC), and the special page mode with the hierarchical I/O data bus lines and multi-purpose-register (MPR) for the column address access time (tCAA). A low power dissipation and wide operating margin are obtained by the improved twisted-bit-line (TBL) architecture with double dummy canceling. The 16 Mb DRAM using these architectures has 38 ns tRAC, 14 ns tCAA and 75 mA power dissipation at the typical condition.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e75-c_10_1267/_p
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@ARTICLE{e75-c_10_1267,
author={Masaki TSUKUDE, Tsukasa OISHI, Kazutami ARIMOTO, Hideto HIDAKA, Kazuyasu FUJISHIMA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A New Array Architecture for 16 Mb DRAMs with Special Page Mode},
year={1992},
volume={E75-C},
number={10},
pages={1267-1274},
abstract={An improved array architecture to realize fast access, low power dissipation, and wide operating margin, for the 16 Mbit DRAM is proposed. A high speed access is obtained by the fully embedded sense drive scheme for the RAS access time (tRAC), and the special page mode with the hierarchical I/O data bus lines and multi-purpose-register (MPR) for the column address access time (tCAA). A low power dissipation and wide operating margin are obtained by the improved twisted-bit-line (TBL) architecture with double dummy canceling. The 16 Mb DRAM using these architectures has 38 ns tRAC, 14 ns tCAA and 75 mA power dissipation at the typical condition.},
keywords={},
doi={},
ISSN={},
month={October},}
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TY - JOUR
TI - A New Array Architecture for 16 Mb DRAMs with Special Page Mode
T2 - IEICE TRANSACTIONS on Electronics
SP - 1267
EP - 1274
AU - Masaki TSUKUDE
AU - Tsukasa OISHI
AU - Kazutami ARIMOTO
AU - Hideto HIDAKA
AU - Kazuyasu FUJISHIMA
PY - 1992
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E75-C
IS - 10
JA - IEICE TRANSACTIONS on Electronics
Y1 - October 1992
AB - An improved array architecture to realize fast access, low power dissipation, and wide operating margin, for the 16 Mbit DRAM is proposed. A high speed access is obtained by the fully embedded sense drive scheme for the RAS access time (tRAC), and the special page mode with the hierarchical I/O data bus lines and multi-purpose-register (MPR) for the column address access time (tCAA). A low power dissipation and wide operating margin are obtained by the improved twisted-bit-line (TBL) architecture with double dummy canceling. The 16 Mb DRAM using these architectures has 38 ns tRAC, 14 ns tCAA and 75 mA power dissipation at the typical condition.
ER -
English
