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Kazutami ARIMOTO Toshihiro HATTORI Hidehiro TAKATA Atsushi HASEGAWA Toru SHIMIZU
Many embedded system application in ubiquitous network strongly require the high performance SoC with overcoming the physical limitations in the advanced CMOS. To develop these SoC, the continuous design efforts have been done. The initial efforts are the primitive level circuit technique and power switching control method for suppressing the standby currents. However, the additional physical limitations and system enhancements becomes main factors, the new design efforts have been proposed. These design efforts are the application-oriented technologies from the system level to device level. This paper introduces the self voltage controlled technique to cancel the PVT (process, voltage, and temperature) variation, power distribution and power management for cellular phone application, parallel algorithm and optimized layout DSP, and massively parallel fine-grained SIMD processor for next multimedia application. The high performance SoC for the embedded are achieved by providing the components of the system level IPs and making the application oriented SoC platform.
Kunio UCHIYAMA Fumio ARAKAWA Yasuhiko SAITO Koki NOGUCHI Atsushi HASEGAWA Shinichi YOSHIOKA Naohiko IRIE Takeshi KITAHARA Mark DEBBAGE Andy STURGES
A 64-bit architecture for an embedded processor targeted for next-generation digital consumer products has been developed. It has dual-mode instruction sets and is optimized for high multimedia performance, provided by SIMD/floating-point vector instructions in 32-bit length ISA, and small code size, provided by a conventional 16-bit length ISA. Large register files, (6464b and 6432b), a split-branch mechanism, and virtual cache are also adopted in the architecture. A 714MIPS/9.6 GOPS/400 MHz processor core with the 64-bit architecture and a system LSI containing the core are developed using 0.15-µm technology. The LSI includes a 3.2 GB/sec high-bandwidth on-chip bus, a high-speed DRAM interface, a SRAM/Flash/ROM/Multiplexed-bus interface, and a 66 MHz PCI interface that provide the performance required for next-generation multimedia applications.
Xiaomin WANG Daisuke KUNIMATSU Tatsushi HASEGAWA Akira SUZUKI
We demonstrate the wide-band (> 25-nm) long-distance (> 1000-km) chromatic dispersion compensation by midway spectral inversion (MSI) using a periodically-polled LiNbO3 device. In order to achieve a flat zero net dispersion, the fourth order dispersion of the single-mode fibers is canceled by MSI, while the third order dispersion is compensated for by the negative slope dispersion compensation fiber (NS-DCF). The second order dispersion is canceled out by both. The long distance propagation is realized by a double recirculation-loop system. A very flat zero dispersion is measured for the first time for over 1000-km single-mode fiber propagation with MSI dispersion compensation.
Shin-ichi WAKABAYASHI Asako BABA Hitomi MORIYA Xiaomin WANG Tatsushi HASEGAWA Akira SUZUKI
We have developed the tunable dispersion compensator based on two twin linearly chirped fiber Bragg gratings with various temperature gradients. Controlling the temperature gradient over one of the twin fiber Bragg gratings by Peltier elements, the dispersion and the dispersion slope were changed independently and continuously. The dispersion and dispersion slope compensator has a large bandwidth of 8 nm and low group-delay ripple of < 4 ps in its chirped fiber Bragg gratings. We experimentally demonstrated a precise controllability of the dispersion and the dispersion slope using linear and parabolic temperature gradient. The dispersion and the dispersion slope changes were achieved continuously with -0.67 ps/nm/ and -0.14 ps/nm2/. The transmission characteristics of the dispersion slope compensation were examined using ultra short pulses in the fiber link. When the total dispersion was zero, the distorted pulse was restored back and the tail was significantly suppressed. 160 Gbit/s signals were also demonstrated over 140 km within 1 dB power penalty by using the dispersion slope compensator.
Naohiko IRIE Fumio ARAKAWA Kunio UCHIYAMA Shinichi YOSHIOKA Atsushi HASEGAWA Kevin IADONATE Mark DEBBAGE David SHEPHERD Margaret GEARTY
An embedded processor core using split branch architecture has been developed. This processor core targets 400 MHz using 0.18 µm technology, and its higher frequency needs deeper pipeline than the conventional processor. To solve the increasing branch penalty problem caused by a deeper pipeline, this processor takes an active preload mechanism to preload the target instructions to internal buffers in order to hide the instruction cache latency. The processor also uses multiple instruction buffers to reduce branch penalty cycles of branch misprediction. The performance estimation result shows that about 70% of branch overhead cycles can be reduced from the conventional implementation. The area for this branch mechanism consumes only 1% of the total core, which is smaller than the conventional branch target buffer (BTB) scheme, and helps to achieve low power and low cost.