Accomplishment of At-Speed BISR for Embedded DRAMs
Summary :
The increase of test time of embedded DRAMs (e-DRAM) is one of the key issues of System-on-chip (SOC) device test. This paper proposes to put the repair analysis function on chip as Built In Self Repair (BISR). BISR is performed at 166 MHz as at-speed of e-DRAM with using low cost automatic test equipment (ATE). The area of the BISR is 1.7 mm2. Using error storage table form contributes to realize small area penalty of repair analysis function. e-DRAM function test time by BISR was about 20% less than the conventional method at wafer level testing. Moreover, representative samples are produced to confirm repair analysis ability. The results show that all of the samples are actually repaired by repair information generated by BISR.
- Publication
- IEICE TRANSACTIONS on Information Vol.E85-D No.10 pp.1498-1505
- Publication Date
- 2002/10/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on Test and Verification of VLSI)
- Category
- BIST
Authors
Yoshihiro NAGURA
Yoshinori FUJIWARA
Katsuya FURUE
Ryuji OHMURA
Tatsunori KOMOIKE
Takenori OKITAKA
Tetsushi TANIZAKI
Katsumi DOSAKA
Kazutami ARIMOTO
Yukiyoshi KODA
Tetsuo TADA
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Yoshihiro NAGURA, Yoshinori FUJIWARA, Katsuya FURUE, Ryuji OHMURA, Tatsunori KOMOIKE, Takenori OKITAKA, Tetsushi TANIZAKI, Katsumi DOSAKA, Kazutami ARIMOTO, Yukiyoshi KODA, Tetsuo TADA, "Accomplishment of At-Speed BISR for Embedded DRAMs" in IEICE TRANSACTIONS on Information,
vol. E85-D, no. 10, pp. 1498-1505, October 2002, doi: .
Abstract: The increase of test time of embedded DRAMs (e-DRAM) is one of the key issues of System-on-chip (SOC) device test. This paper proposes to put the repair analysis function on chip as Built In Self Repair (BISR). BISR is performed at 166 MHz as at-speed of e-DRAM with using low cost automatic test equipment (ATE). The area of the BISR is 1.7 mm2. Using error storage table form contributes to realize small area penalty of repair analysis function. e-DRAM function test time by BISR was about 20% less than the conventional method at wafer level testing. Moreover, representative samples are produced to confirm repair analysis ability. The results show that all of the samples are actually repaired by repair information generated by BISR.
URL: https://global.ieice.org/en_transactions/information/10.1587/e85-d_10_1498/_p
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@ARTICLE{e85-d_10_1498,
author={Yoshihiro NAGURA, Yoshinori FUJIWARA, Katsuya FURUE, Ryuji OHMURA, Tatsunori KOMOIKE, Takenori OKITAKA, Tetsushi TANIZAKI, Katsumi DOSAKA, Kazutami ARIMOTO, Yukiyoshi KODA, Tetsuo TADA, },
journal={IEICE TRANSACTIONS on Information},
title={Accomplishment of At-Speed BISR for Embedded DRAMs},
year={2002},
volume={E85-D},
number={10},
pages={1498-1505},
abstract={The increase of test time of embedded DRAMs (e-DRAM) is one of the key issues of System-on-chip (SOC) device test. This paper proposes to put the repair analysis function on chip as Built In Self Repair (BISR). BISR is performed at 166 MHz as at-speed of e-DRAM with using low cost automatic test equipment (ATE). The area of the BISR is 1.7 mm2. Using error storage table form contributes to realize small area penalty of repair analysis function. e-DRAM function test time by BISR was about 20% less than the conventional method at wafer level testing. Moreover, representative samples are produced to confirm repair analysis ability. The results show that all of the samples are actually repaired by repair information generated by BISR.},
keywords={},
doi={},
ISSN={},
month={October},}
Copy
TY - JOUR
TI - Accomplishment of At-Speed BISR for Embedded DRAMs
T2 - IEICE TRANSACTIONS on Information
SP - 1498
EP - 1505
AU - Yoshihiro NAGURA
AU - Yoshinori FUJIWARA
AU - Katsuya FURUE
AU - Ryuji OHMURA
AU - Tatsunori KOMOIKE
AU - Takenori OKITAKA
AU - Tetsushi TANIZAKI
AU - Katsumi DOSAKA
AU - Kazutami ARIMOTO
AU - Yukiyoshi KODA
AU - Tetsuo TADA
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E85-D
IS - 10
JA - IEICE TRANSACTIONS on Information
Y1 - October 2002
AB - The increase of test time of embedded DRAMs (e-DRAM) is one of the key issues of System-on-chip (SOC) device test. This paper proposes to put the repair analysis function on chip as Built In Self Repair (BISR). BISR is performed at 166 MHz as at-speed of e-DRAM with using low cost automatic test equipment (ATE). The area of the BISR is 1.7 mm2. Using error storage table form contributes to realize small area penalty of repair analysis function. e-DRAM function test time by BISR was about 20% less than the conventional method at wafer level testing. Moreover, representative samples are produced to confirm repair analysis ability. The results show that all of the samples are actually repaired by repair information generated by BISR.
ER -
English
