The increase of test time of embedded DRAMs (e-DRAM) is one of the key issues of System-on-chip (SOC) device test. This paper proposes to put the repair analysis function on chip as Built In Self Repair (BISR). BISR is performed at 166 MHz as at-speed of e-DRAM with using low cost automatic test equipment (ATE). The area of the BISR is 1.7 mm2. Using error storage table form contributes to realize small area penalty of repair analysis function. e-DRAM function test time by BISR was about 20% less than the conventional method at wafer level testing. Moreover, representative samples are produced to confirm repair analysis ability. The results show that all of the samples are actually repaired by repair information generated by BISR.

A test system with a fuzzy logic controller is proposed to assure stable outgoing quality as well as to raise throughput. The test system controls the number of items under test in accordance with fuzzy information as well as statistical information about incoming quality and outgoing quality. First, an algorithm, minimum-minimum-the center of gravity-weighted mean method, is studied with both fuzzy reasoning rules and membership functions which are used for the control. Second, characteristics of the test system are verified and examined with computer simulations so that the fuzzy logic control rules are determined to realize sufficient sensitivity to process changes. Third, the control rules are installed in the test management processor which commands test equipment for testing very large scale integrated circuits, with programming language C. The authors have obtained satisfactory results through a trial run using a series of lots of 16 bit micro controller units in an IC manufacturing factory. Finally, they study the stability condition of the fuzzy test system.