The development of an extremely efficient packet inspection algorithm for lookup engines is important in order to realize high throughput and to lower energy dissipation. In this paper, we propose a new lookup engine based on a combination of a mismatch detection circuit and a linked-list hash table. The engine has an automatic rule registration and deletion function; the results are that it is only necessary to input rules, and the various tables included in the circuits, such as the Mismatch Table, Index Table, and Rule Table, will be automatically configured using the embedded hardware. This function utilizes a match/mismatch assessment for normal packet inspection operations. An experimental chip was fabricated using 40-nm 8-metal CMOS process technology. The chip operates at a frequency of 100MHz under a power supply voltage of VDD =1.1V. A throughput of 100Mpacket/s (=51.2Gb/s) is obtained at an operating frequency of 100MHz, which is three times greater than the throughput of 33Mpacket/s obtained with a conventional lookup engine without a mismatch detection circuit. The measured energy dissipation was a 1.58pJ/b·Search.

A Field Programmable Sequencer and Memory (FPSM), which is a programmable unit exclusively optimized for peripherals on a micro controller unit, is proposed. The FPSM functions as not only the peripherals but also the standard built-in memory. The FPSM provides easier programmability with a smaller area overhead, especially when compared with the FPGA. The FPSM is implemented on the FPGA and the programmability and performance for basic peripherals such as the 8 bit counter and 8 bit accuracy Pulse Width Modulation are emulated on the FPGA. Furthermore, the FPSM core with a 4K bit SRAM is fabricated in 0.18µm 5 metal CMOS process technology. The FPSM is an half the area of FPGA, its power consumption is less than one-fifth.

The aim of this study is to develop a new whole-body averaged specific absorption rate (SAR) estimation method based on the external-cylindrical field scanning technique. This technique is adopted with the goal of simplifying the dosimetry estimation of human phantoms that have different postures or sizes. An experimental scaled model system is constructed. In order to examine the validity of the proposed method for realistic human models, we discuss the pros and cons of measurements and numerical analyses based on the finite-difference time-domain (FDTD) method. We consider the anatomical European human phantoms and plane-wave in the 2 GHz mobile phone frequency band. The measured whole-body averaged SAR results obtained by the proposed method are compared with the results of the FDTD analyses.

The purpose of this study is to establish a whole-body averaged specific absorption rate (WB-SAR) estimation method using the power absorbed by humans; a cylindrical-external field scanning technique is used to measure the radiated RF (radio-frequency) power. This technique is adopted with the goal of simplifying the estimation of the exposure dosimetry of humans who have different postures and/or sizes. In this paper, to validate the proposed measurement method, we subject numerical human phantom models and cylindrical scanning conditions to FDTD analysis. We design a radiation system that uses a dielectric lens to achieve plane-wave irradiation of tested human phantoms in order to develop an experimental WB-SAR measurement system for UHF far-field exposure condition. In addition, we use a constructed SAR measurement system to confirm absorbed power estimations of simple geometrical phantoms and so estimate measurement error of the measurement system. Finally, we discuss the measurement results of WB-SARs for male adult and child human phantom models.

The parallel branching program machine (PBM128) consists of 128 branching program machines (BMs) and a programmable interconnection. To represent logic functions on BMs, we use quaternary decision diagrams. To evaluate functions, we use 3-address quaternary branch instructions. We realized many benchmark functions on the PBM128, and compared its memory size, computation time, and power consumption with the Intel's Core2Duo microprocessor. The PBM128 requires approximately a quarter of the memory for the Core2Duo, and is 21.4-96.1 times faster than the Core2Duo. It dissipates a quarter of the power of the Core2Duo. Also, we realized packet filters such as an access controller and a firewall, and compared their performance with software on the Core2Duo. For these packet filters, the PBM128 requires approximately 17% of the memory for the Core2Duo, and is 21.3-23.7 times faster than the Core2Duo.

This paper reports on X-band Gallium Nitride (GaN) chipsets for cost-effective 20W transmit-receive (T/R) modules. The chipset components include a GaN-on-Si monolithic microwave integrated circuit (MMIC) driver amplifier (DA), a GaN-on-SiC high power amplifier (HPA) with GaAs matching circuits, a high-gain GaN-on-Si HPA with a GaAs output matching circuit, and a GaN-on-Si MMIC switch (SW). By utilizing either combination of the DA or single high-gain HPA, the configurations of two T/R module types can be realized. The GaN-on-Si MMIC DA demonstrates an output power of 6.4-7.4W, an associate gain of 22.3-24.6dB and a power added efficiency (PAE) of 32-36% over 9.0-11.0GHz. A GaN-on-SiC HPA with GaAs matching circuits exhibited an output power of 20-28W, associate gain of 7.8-10.7dB, and a PAE of 40-56% over 9.0-11.0GHz. The high-gain GaN-on-Si HPA with a GaAs output matching circuit exhibits an output power of 15-30W, associate gain of 27-30dB, and PAE of 26-33% over 9.0-11.0GHz. The GaN-on-Si MMIC switch demonstrates insertion losses of 1.1-1.3dB and isolation of 10.1-14.7dB over 8.0-11.5GHz. By employing cost-effective circuit configurations, the costs of these chipsets are estimated to be about half that of conventional chipsets.

This paper first reviews the trends of VLSI design, focusing on the power dissipation and programmability. Then, we show the advantage of Quarternary Decision Diagrams (QDDs) in representing and evaluating logic functions. That is, we show how QDDs are used to implement QDD machines, which yield high-speed implementations. We compare QDD machines with binary decision diagram (BDD) machines, and show a speed improvement of 1.28-2.02 times when QDDs are chosen. We consider 1-and 2-address BDD machines, and 3- and 4-address QDD machines, and we show a method to minimize the number of instructions.