IEICE TRANSACTIONS on Information
A Quaternary Decision Diagram Machine: Optimization of Its Code
Summary :
This paper first reviews the trends of VLSI design, focusing on the power dissipation and programmability. Then, we show the advantage of Quarternary Decision Diagrams (QDDs) in representing and evaluating logic functions. That is, we show how QDDs are used to implement QDD machines, which yield high-speed implementations. We compare QDD machines with binary decision diagram (BDD) machines, and show a speed improvement of 1.28-2.02 times when QDDs are chosen. We consider 1-and 2-address BDD machines, and 3- and 4-address QDD machines, and we show a method to minimize the number of instructions.
- Publication
- IEICE TRANSACTIONS on Information Vol.E93-D No.8 pp.2026-2035
- Publication Date
- 2010/08/01
- Publicized
- Online ISSN
- 1745-1361
- DOI
- 10.1587/transinf.E93.D.2026
- Type of Manuscript
- Special Section INVITED PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
- Category
Authors
Keyword
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Tsutomu SASAO, Hiroki NAKAHARA, Munehiro MATSUURA, Yoshifumi KAWAMURA, Jon T. BUTLER, "A Quaternary Decision Diagram Machine: Optimization of Its Code" in IEICE TRANSACTIONS on Information,
vol. E93-D, no. 8, pp. 2026-2035, August 2010, doi: 10.1587/transinf.E93.D.2026.
Abstract: This paper first reviews the trends of VLSI design, focusing on the power dissipation and programmability. Then, we show the advantage of Quarternary Decision Diagrams (QDDs) in representing and evaluating logic functions. That is, we show how QDDs are used to implement QDD machines, which yield high-speed implementations. We compare QDD machines with binary decision diagram (BDD) machines, and show a speed improvement of 1.28-2.02 times when QDDs are chosen. We consider 1-and 2-address BDD machines, and 3- and 4-address QDD machines, and we show a method to minimize the number of instructions.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E93.D.2026/_p
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@ARTICLE{e93-d_8_2026,
author={Tsutomu SASAO, Hiroki NAKAHARA, Munehiro MATSUURA, Yoshifumi KAWAMURA, Jon T. BUTLER, },
journal={IEICE TRANSACTIONS on Information},
title={A Quaternary Decision Diagram Machine: Optimization of Its Code},
year={2010},
volume={E93-D},
number={8},
pages={2026-2035},
abstract={This paper first reviews the trends of VLSI design, focusing on the power dissipation and programmability. Then, we show the advantage of Quarternary Decision Diagrams (QDDs) in representing and evaluating logic functions. That is, we show how QDDs are used to implement QDD machines, which yield high-speed implementations. We compare QDD machines with binary decision diagram (BDD) machines, and show a speed improvement of 1.28-2.02 times when QDDs are chosen. We consider 1-and 2-address BDD machines, and 3- and 4-address QDD machines, and we show a method to minimize the number of instructions.},
keywords={},
doi={10.1587/transinf.E93.D.2026},
ISSN={1745-1361},
month={August},}
Copy
TY - JOUR
TI - A Quaternary Decision Diagram Machine: Optimization of Its Code
T2 - IEICE TRANSACTIONS on Information
SP - 2026
EP - 2035
AU - Tsutomu SASAO
AU - Hiroki NAKAHARA
AU - Munehiro MATSUURA
AU - Yoshifumi KAWAMURA
AU - Jon T. BUTLER
PY - 2010
DO - 10.1587/transinf.E93.D.2026
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E93-D
IS - 8
JA - IEICE TRANSACTIONS on Information
Y1 - August 2010
AB - This paper first reviews the trends of VLSI design, focusing on the power dissipation and programmability. Then, we show the advantage of Quarternary Decision Diagrams (QDDs) in representing and evaluating logic functions. That is, we show how QDDs are used to implement QDD machines, which yield high-speed implementations. We compare QDD machines with binary decision diagram (BDD) machines, and show a speed improvement of 1.28-2.02 times when QDDs are chosen. We consider 1-and 2-address BDD machines, and 3- and 4-address QDD machines, and we show a method to minimize the number of instructions.
ER -
English
