An Exact Leading Non-Zero Detector for a Floating-Point Unit
Summary :
Parallel execution of the carry propagate adder (CPA) and leading non-zero (LNZ) detector that processes the CPA result is a common way to reduce the latencies of floating-point instructions. However, the conventional methods usually cause one-bit errors. We developed an exact LNZ detection circuit operating in parallel with the CPA. The circuit is implemented in the floating-point unit of our newly developed embedded processor core. Circuit simulation results show that the LNZ circuit has a similar speed to the CPA, and it contributes to make a small low-power FPU for an embedded processor core.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E88-C No.4 pp.570-575
- Publication Date
- 2005/04/01
- Publicized
- Online ISSN
- DOI
- 10.1093/ietele/e88-c.4.570
- Type of Manuscript
- Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP)
- Category
- Digital
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Fumio ARAKAWA, Tomoichi HAYASHI, Masakazu NISHIBORI, "An Exact Leading Non-Zero Detector for a Floating-Point Unit" in IEICE TRANSACTIONS on Electronics,
vol. E88-C, no. 4, pp. 570-575, April 2005, doi: 10.1093/ietele/e88-c.4.570.
Abstract: Parallel execution of the carry propagate adder (CPA) and leading non-zero (LNZ) detector that processes the CPA result is a common way to reduce the latencies of floating-point instructions. However, the conventional methods usually cause one-bit errors. We developed an exact LNZ detection circuit operating in parallel with the CPA. The circuit is implemented in the floating-point unit of our newly developed embedded processor core. Circuit simulation results show that the LNZ circuit has a similar speed to the CPA, and it contributes to make a small low-power FPU for an embedded processor core.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e88-c.4.570/_p
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@ARTICLE{e88-c_4_570,
author={Fumio ARAKAWA, Tomoichi HAYASHI, Masakazu NISHIBORI, },
journal={IEICE TRANSACTIONS on Electronics},
title={An Exact Leading Non-Zero Detector for a Floating-Point Unit},
year={2005},
volume={E88-C},
number={4},
pages={570-575},
abstract={Parallel execution of the carry propagate adder (CPA) and leading non-zero (LNZ) detector that processes the CPA result is a common way to reduce the latencies of floating-point instructions. However, the conventional methods usually cause one-bit errors. We developed an exact LNZ detection circuit operating in parallel with the CPA. The circuit is implemented in the floating-point unit of our newly developed embedded processor core. Circuit simulation results show that the LNZ circuit has a similar speed to the CPA, and it contributes to make a small low-power FPU for an embedded processor core.},
keywords={},
doi={10.1093/ietele/e88-c.4.570},
ISSN={},
month={April},}
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TY - JOUR
TI - An Exact Leading Non-Zero Detector for a Floating-Point Unit
T2 - IEICE TRANSACTIONS on Electronics
SP - 570
EP - 575
AU - Fumio ARAKAWA
AU - Tomoichi HAYASHI
AU - Masakazu NISHIBORI
PY - 2005
DO - 10.1093/ietele/e88-c.4.570
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E88-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2005
AB - Parallel execution of the carry propagate adder (CPA) and leading non-zero (LNZ) detector that processes the CPA result is a common way to reduce the latencies of floating-point instructions. However, the conventional methods usually cause one-bit errors. We developed an exact LNZ detection circuit operating in parallel with the CPA. The circuit is implemented in the floating-point unit of our newly developed embedded processor core. Circuit simulation results show that the LNZ circuit has a similar speed to the CPA, and it contributes to make a small low-power FPU for an embedded processor core.
ER -
English
