IEICE TRANSACTIONS on Electronics
Low-Power Design of High-Speed A/D Converters
Summary :
In this paper, low-power design techniques of high-speed A/D converters are reviewed and discussed. Pipeline and parallel-pipeline architectures are treated as these are dominant architectures when required high sampling rate and high resolution with reasonable power dissipation. A systematic approach to the power optimization of pipeline and parallel pipeline ADC's is introduced based on models of noise analysis and response time of a building block in the multiple-stage pipeline ADC. Finally, the theoretical minimum of required power as functions of the sampling rate, resolution and SNR is discussed. The analysis shows that, with the developments of new circuits and systems to approach to the minimum, the power can be further reduced by a factor of more than 1/10 without changing the basic architectures.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E88-C No.4 pp.468-478
- Publication Date
- 2005/04/01
- Publicized
- Online ISSN
- DOI
- 10.1093/ietele/e88-c.4.468
- Type of Manuscript
- Special Section INVITED PAPER (Special Section on Low-Power LSI and Low-Power IP)
- Category
Authors
Keyword
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Shoji KAWAHITO, Kazutaka HONDA, Masanori FURUTA, Nobuhiro KAWAI, Daisuke MIYAZAKI, "Low-Power Design of High-Speed A/D Converters" in IEICE TRANSACTIONS on Electronics,
vol. E88-C, no. 4, pp. 468-478, April 2005, doi: 10.1093/ietele/e88-c.4.468.
Abstract: In this paper, low-power design techniques of high-speed A/D converters are reviewed and discussed. Pipeline and parallel-pipeline architectures are treated as these are dominant architectures when required high sampling rate and high resolution with reasonable power dissipation. A systematic approach to the power optimization of pipeline and parallel pipeline ADC's is introduced based on models of noise analysis and response time of a building block in the multiple-stage pipeline ADC. Finally, the theoretical minimum of required power as functions of the sampling rate, resolution and SNR is discussed. The analysis shows that, with the developments of new circuits and systems to approach to the minimum, the power can be further reduced by a factor of more than 1/10 without changing the basic architectures.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e88-c.4.468/_p
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@ARTICLE{e88-c_4_468,
author={Shoji KAWAHITO, Kazutaka HONDA, Masanori FURUTA, Nobuhiro KAWAI, Daisuke MIYAZAKI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Low-Power Design of High-Speed A/D Converters},
year={2005},
volume={E88-C},
number={4},
pages={468-478},
abstract={In this paper, low-power design techniques of high-speed A/D converters are reviewed and discussed. Pipeline and parallel-pipeline architectures are treated as these are dominant architectures when required high sampling rate and high resolution with reasonable power dissipation. A systematic approach to the power optimization of pipeline and parallel pipeline ADC's is introduced based on models of noise analysis and response time of a building block in the multiple-stage pipeline ADC. Finally, the theoretical minimum of required power as functions of the sampling rate, resolution and SNR is discussed. The analysis shows that, with the developments of new circuits and systems to approach to the minimum, the power can be further reduced by a factor of more than 1/10 without changing the basic architectures.},
keywords={},
doi={10.1093/ietele/e88-c.4.468},
ISSN={},
month={April},}
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TY - JOUR
TI - Low-Power Design of High-Speed A/D Converters
T2 - IEICE TRANSACTIONS on Electronics
SP - 468
EP - 478
AU - Shoji KAWAHITO
AU - Kazutaka HONDA
AU - Masanori FURUTA
AU - Nobuhiro KAWAI
AU - Daisuke MIYAZAKI
PY - 2005
DO - 10.1093/ietele/e88-c.4.468
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E88-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2005
AB - In this paper, low-power design techniques of high-speed A/D converters are reviewed and discussed. Pipeline and parallel-pipeline architectures are treated as these are dominant architectures when required high sampling rate and high resolution with reasonable power dissipation. A systematic approach to the power optimization of pipeline and parallel pipeline ADC's is introduced based on models of noise analysis and response time of a building block in the multiple-stage pipeline ADC. Finally, the theoretical minimum of required power as functions of the sampling rate, resolution and SNR is discussed. The analysis shows that, with the developments of new circuits and systems to approach to the minimum, the power can be further reduced by a factor of more than 1/10 without changing the basic architectures.
ER -
English
