The Umbrella Cell: A High-Density 2T Cell for SOC Applications
Summary :
To realize a high-density on-chip memory, the authors have proposed a novel logic-process-compatible memory cell. This cell consists of two logic transistors, and placing a planar MIM (metal insulator metal) capacitor on a copper wire above the transistors produces a memory area of 26 F2, which is approximately 60% smaller than a 6T SRAM cell. A suitable cell-bias design and a dual precharge scheme solve the coupling problem inherent in the cell and allow standard logic transistors to be used. This cell--applying the proposed schemes--can handle 10-ns cycle time at a bit-line voltage of 0.7 V. The random cycle is about three times faster than that of a conventional VBL precharge scheme. These results indicate that the umbrella cell is a strong candidate for providing a high-density memory for SOC applications.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E88-C No.4 pp.614-621
- Publication Date
- 2005/04/01
- Publicized
- Online ISSN
- DOI
- 10.1093/ietele/e88-c.4.614
- Type of Manuscript
- Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP)
- Category
- Memory
Authors
Keyword
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Satoru AKIYAMA, Takao WATANABE, Nobuhiro OODAIRA, Tsuyoshi ISHIKAWA, Digh HISAMOTO, "The Umbrella Cell: A High-Density 2T Cell for SOC Applications" in IEICE TRANSACTIONS on Electronics,
vol. E88-C, no. 4, pp. 614-621, April 2005, doi: 10.1093/ietele/e88-c.4.614.
Abstract: To realize a high-density on-chip memory, the authors have proposed a novel logic-process-compatible memory cell. This cell consists of two logic transistors, and placing a planar MIM (metal insulator metal) capacitor on a copper wire above the transistors produces a memory area of 26 F2, which is approximately 60% smaller than a 6T SRAM cell. A suitable cell-bias design and a dual precharge scheme solve the coupling problem inherent in the cell and allow standard logic transistors to be used. This cell--applying the proposed schemes--can handle 10-ns cycle time at a bit-line voltage of 0.7 V. The random cycle is about three times faster than that of a conventional VBL precharge scheme. These results indicate that the umbrella cell is a strong candidate for providing a high-density memory for SOC applications.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e88-c.4.614/_p
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@ARTICLE{e88-c_4_614,
author={Satoru AKIYAMA, Takao WATANABE, Nobuhiro OODAIRA, Tsuyoshi ISHIKAWA, Digh HISAMOTO, },
journal={IEICE TRANSACTIONS on Electronics},
title={The Umbrella Cell: A High-Density 2T Cell for SOC Applications},
year={2005},
volume={E88-C},
number={4},
pages={614-621},
abstract={To realize a high-density on-chip memory, the authors have proposed a novel logic-process-compatible memory cell. This cell consists of two logic transistors, and placing a planar MIM (metal insulator metal) capacitor on a copper wire above the transistors produces a memory area of 26 F2, which is approximately 60% smaller than a 6T SRAM cell. A suitable cell-bias design and a dual precharge scheme solve the coupling problem inherent in the cell and allow standard logic transistors to be used. This cell--applying the proposed schemes--can handle 10-ns cycle time at a bit-line voltage of 0.7 V. The random cycle is about three times faster than that of a conventional VBL precharge scheme. These results indicate that the umbrella cell is a strong candidate for providing a high-density memory for SOC applications.},
keywords={},
doi={10.1093/ietele/e88-c.4.614},
ISSN={},
month={April},}
Copy
TY - JOUR
TI - The Umbrella Cell: A High-Density 2T Cell for SOC Applications
T2 - IEICE TRANSACTIONS on Electronics
SP - 614
EP - 621
AU - Satoru AKIYAMA
AU - Takao WATANABE
AU - Nobuhiro OODAIRA
AU - Tsuyoshi ISHIKAWA
AU - Digh HISAMOTO
PY - 2005
DO - 10.1093/ietele/e88-c.4.614
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E88-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2005
AB - To realize a high-density on-chip memory, the authors have proposed a novel logic-process-compatible memory cell. This cell consists of two logic transistors, and placing a planar MIM (metal insulator metal) capacitor on a copper wire above the transistors produces a memory area of 26 F2, which is approximately 60% smaller than a 6T SRAM cell. A suitable cell-bias design and a dual precharge scheme solve the coupling problem inherent in the cell and allow standard logic transistors to be used. This cell--applying the proposed schemes--can handle 10-ns cycle time at a bit-line voltage of 0.7 V. The random cycle is about three times faster than that of a conventional VBL precharge scheme. These results indicate that the umbrella cell is a strong candidate for providing a high-density memory for SOC applications.
ER -
English
