IEICE TRANSACTIONS on Electronics
A Low-Power Systolic Array Architecture for Block-Matching Motion Estimation
Summary :
This paper proposes a low-power systolic array architecture for a block-matching motion estimation processor IP for portable and high-resolution video applications. The architecture features a ring-connected processing element (PE) array to reduce both computation cycles and memory access cycles at the same time, allowing lower power characteristics. The feature of low memory access cycles allows concurrent operation of a half-pel processing unit with no extra cache. Furthermore, the architecture allows various summation schemes for absolute difference values. For that reason, it is applicable to various video coding modes such as the adaptive field/frame mode in MPEG2 and multiple macroblock mode in H.264. When the architecture is introduced to a design of a MPEG2 MP@HL motion estimation processor VLSI, the power consumption of the VLSI is reduced by 45-73% in comparison to cases with conventional architectures for motion estimation.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E88-C No.4 pp.559-569
- Publication Date
- 2005/04/01
- Publicized
- Online ISSN
- DOI
- 10.1093/ietele/e88-c.4.559
- Type of Manuscript
- Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP)
- Category
- Digital
Authors
Keyword
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Junichi MIYAKOSHI, Yuichiro MURACHI, Koji HAMANO, Tetsuro MATSUNO, Masayuki MIYAMA, Masahiko YOSHIMOTO, "A Low-Power Systolic Array Architecture for Block-Matching Motion Estimation" in IEICE TRANSACTIONS on Electronics,
vol. E88-C, no. 4, pp. 559-569, April 2005, doi: 10.1093/ietele/e88-c.4.559.
Abstract: This paper proposes a low-power systolic array architecture for a block-matching motion estimation processor IP for portable and high-resolution video applications. The architecture features a ring-connected processing element (PE) array to reduce both computation cycles and memory access cycles at the same time, allowing lower power characteristics. The feature of low memory access cycles allows concurrent operation of a half-pel processing unit with no extra cache. Furthermore, the architecture allows various summation schemes for absolute difference values. For that reason, it is applicable to various video coding modes such as the adaptive field/frame mode in MPEG2 and multiple macroblock mode in H.264. When the architecture is introduced to a design of a MPEG2 MP@HL motion estimation processor VLSI, the power consumption of the VLSI is reduced by 45-73% in comparison to cases with conventional architectures for motion estimation.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e88-c.4.559/_p
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@ARTICLE{e88-c_4_559,
author={Junichi MIYAKOSHI, Yuichiro MURACHI, Koji HAMANO, Tetsuro MATSUNO, Masayuki MIYAMA, Masahiko YOSHIMOTO, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Low-Power Systolic Array Architecture for Block-Matching Motion Estimation},
year={2005},
volume={E88-C},
number={4},
pages={559-569},
abstract={This paper proposes a low-power systolic array architecture for a block-matching motion estimation processor IP for portable and high-resolution video applications. The architecture features a ring-connected processing element (PE) array to reduce both computation cycles and memory access cycles at the same time, allowing lower power characteristics. The feature of low memory access cycles allows concurrent operation of a half-pel processing unit with no extra cache. Furthermore, the architecture allows various summation schemes for absolute difference values. For that reason, it is applicable to various video coding modes such as the adaptive field/frame mode in MPEG2 and multiple macroblock mode in H.264. When the architecture is introduced to a design of a MPEG2 MP@HL motion estimation processor VLSI, the power consumption of the VLSI is reduced by 45-73% in comparison to cases with conventional architectures for motion estimation.},
keywords={},
doi={10.1093/ietele/e88-c.4.559},
ISSN={},
month={April},}
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TY - JOUR
TI - A Low-Power Systolic Array Architecture for Block-Matching Motion Estimation
T2 - IEICE TRANSACTIONS on Electronics
SP - 559
EP - 569
AU - Junichi MIYAKOSHI
AU - Yuichiro MURACHI
AU - Koji HAMANO
AU - Tetsuro MATSUNO
AU - Masayuki MIYAMA
AU - Masahiko YOSHIMOTO
PY - 2005
DO - 10.1093/ietele/e88-c.4.559
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E88-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2005
AB - This paper proposes a low-power systolic array architecture for a block-matching motion estimation processor IP for portable and high-resolution video applications. The architecture features a ring-connected processing element (PE) array to reduce both computation cycles and memory access cycles at the same time, allowing lower power characteristics. The feature of low memory access cycles allows concurrent operation of a half-pel processing unit with no extra cache. Furthermore, the architecture allows various summation schemes for absolute difference values. For that reason, it is applicable to various video coding modes such as the adaptive field/frame mode in MPEG2 and multiple macroblock mode in H.264. When the architecture is introduced to a design of a MPEG2 MP@HL motion estimation processor VLSI, the power consumption of the VLSI is reduced by 45-73% in comparison to cases with conventional architectures for motion estimation.
ER -
English
