Dynamic Voltage and Frequency Management for a Low-Power Embedded Microprocessor
Summary :
In this paper, a Dynamic Voltage and Frequency Management (DVFM) scheme introduced in a microprocessor for handheld devices with wideband embedded DRAM is reported. Our DVFM scheme reduces the power consumption effectively by cooperation of the autonomous clock frequency control and the adaptive supply voltage control. The clock frequency is controlled using hardware activity information to determine the minimum value required by the current processor load. This clock frequency control is realized without special power management software. The supply voltage is controlled according to the delay information provided from a delay synthesizer circuit, which consists of three programmable delay components, gate delay, RC delay and a rise/fall delay. The delay synthesizer circuit emulates the critical-path delay within 4% voltage accuracy over the full range of process deviation and voltage. This accurate tracking ability realizes the supply voltage scaling according to the fluctuation of the LSI's characteristic caused by the temperature and process deviation. The DVFM contributes not only the dynamic power reduction, but also the leakage power reduction. This microprocessor, fabricated in 0.18 µm CMOS embedded DRAM technology achieves 82% power reduction in a Personal Information Management scheduler (PIM) application and 40% power reduction in a MPEG4 movie playback application. As process technology shrinks, the DVFM scheme with leakage power compensation effect will become more important realizing in high-performance and low-power mobile consumer applications.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E88-C No.4 pp.520-527
- Publication Date
- 2005/04/01
- Publicized
- Online ISSN
- DOI
- 10.1093/ietele/e88-c.4.520
- Type of Manuscript
- Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP)
- Category
- Digital
Authors
Takahiro SEKI
Satoshi AKUI
Katsunori SENO
Masakatsu NAKAI
Tetsumasa MEGURO
Tetsuo KONDO
Akihiko HASHIGUCHI
Hirokazu KAWAHARA
Kazuo KUMANO
Masayuki SHIMURA
Keyword
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Takahiro SEKI, Satoshi AKUI, Katsunori SENO, Masakatsu NAKAI, Tetsumasa MEGURO, Tetsuo KONDO, Akihiko HASHIGUCHI, Hirokazu KAWAHARA, Kazuo KUMANO, Masayuki SHIMURA, "Dynamic Voltage and Frequency Management for a Low-Power Embedded Microprocessor" in IEICE TRANSACTIONS on Electronics,
vol. E88-C, no. 4, pp. 520-527, April 2005, doi: 10.1093/ietele/e88-c.4.520.
Abstract: In this paper, a Dynamic Voltage and Frequency Management (DVFM) scheme introduced in a microprocessor for handheld devices with wideband embedded DRAM is reported. Our DVFM scheme reduces the power consumption effectively by cooperation of the autonomous clock frequency control and the adaptive supply voltage control. The clock frequency is controlled using hardware activity information to determine the minimum value required by the current processor load. This clock frequency control is realized without special power management software. The supply voltage is controlled according to the delay information provided from a delay synthesizer circuit, which consists of three programmable delay components, gate delay, RC delay and a rise/fall delay. The delay synthesizer circuit emulates the critical-path delay within 4% voltage accuracy over the full range of process deviation and voltage. This accurate tracking ability realizes the supply voltage scaling according to the fluctuation of the LSI's characteristic caused by the temperature and process deviation. The DVFM contributes not only the dynamic power reduction, but also the leakage power reduction. This microprocessor, fabricated in 0.18 µm CMOS embedded DRAM technology achieves 82% power reduction in a Personal Information Management scheduler (PIM) application and 40% power reduction in a MPEG4 movie playback application. As process technology shrinks, the DVFM scheme with leakage power compensation effect will become more important realizing in high-performance and low-power mobile consumer applications.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e88-c.4.520/_p
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@ARTICLE{e88-c_4_520,
author={Takahiro SEKI, Satoshi AKUI, Katsunori SENO, Masakatsu NAKAI, Tetsumasa MEGURO, Tetsuo KONDO, Akihiko HASHIGUCHI, Hirokazu KAWAHARA, Kazuo KUMANO, Masayuki SHIMURA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Dynamic Voltage and Frequency Management for a Low-Power Embedded Microprocessor},
year={2005},
volume={E88-C},
number={4},
pages={520-527},
abstract={In this paper, a Dynamic Voltage and Frequency Management (DVFM) scheme introduced in a microprocessor for handheld devices with wideband embedded DRAM is reported. Our DVFM scheme reduces the power consumption effectively by cooperation of the autonomous clock frequency control and the adaptive supply voltage control. The clock frequency is controlled using hardware activity information to determine the minimum value required by the current processor load. This clock frequency control is realized without special power management software. The supply voltage is controlled according to the delay information provided from a delay synthesizer circuit, which consists of three programmable delay components, gate delay, RC delay and a rise/fall delay. The delay synthesizer circuit emulates the critical-path delay within 4% voltage accuracy over the full range of process deviation and voltage. This accurate tracking ability realizes the supply voltage scaling according to the fluctuation of the LSI's characteristic caused by the temperature and process deviation. The DVFM contributes not only the dynamic power reduction, but also the leakage power reduction. This microprocessor, fabricated in 0.18 µm CMOS embedded DRAM technology achieves 82% power reduction in a Personal Information Management scheduler (PIM) application and 40% power reduction in a MPEG4 movie playback application. As process technology shrinks, the DVFM scheme with leakage power compensation effect will become more important realizing in high-performance and low-power mobile consumer applications.},
keywords={},
doi={10.1093/ietele/e88-c.4.520},
ISSN={},
month={April},}
Copy
TY - JOUR
TI - Dynamic Voltage and Frequency Management for a Low-Power Embedded Microprocessor
T2 - IEICE TRANSACTIONS on Electronics
SP - 520
EP - 527
AU - Takahiro SEKI
AU - Satoshi AKUI
AU - Katsunori SENO
AU - Masakatsu NAKAI
AU - Tetsumasa MEGURO
AU - Tetsuo KONDO
AU - Akihiko HASHIGUCHI
AU - Hirokazu KAWAHARA
AU - Kazuo KUMANO
AU - Masayuki SHIMURA
PY - 2005
DO - 10.1093/ietele/e88-c.4.520
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E88-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2005
AB - In this paper, a Dynamic Voltage and Frequency Management (DVFM) scheme introduced in a microprocessor for handheld devices with wideband embedded DRAM is reported. Our DVFM scheme reduces the power consumption effectively by cooperation of the autonomous clock frequency control and the adaptive supply voltage control. The clock frequency is controlled using hardware activity information to determine the minimum value required by the current processor load. This clock frequency control is realized without special power management software. The supply voltage is controlled according to the delay information provided from a delay synthesizer circuit, which consists of three programmable delay components, gate delay, RC delay and a rise/fall delay. The delay synthesizer circuit emulates the critical-path delay within 4% voltage accuracy over the full range of process deviation and voltage. This accurate tracking ability realizes the supply voltage scaling according to the fluctuation of the LSI's characteristic caused by the temperature and process deviation. The DVFM contributes not only the dynamic power reduction, but also the leakage power reduction. This microprocessor, fabricated in 0.18 µm CMOS embedded DRAM technology achieves 82% power reduction in a Personal Information Management scheduler (PIM) application and 40% power reduction in a MPEG4 movie playback application. As process technology shrinks, the DVFM scheme with leakage power compensation effect will become more important realizing in high-performance and low-power mobile consumer applications.
ER -
English
