This paper discusses propagation delay error, transient response, and power consumption distribution due to inductive effects in optimal buffered on-chip interconnects. Inductive effect is said to be important to consider in deep submicron (DSM) VLSI design. However, study shows that the effect decreases and can be neglected in next technology nodes for such conditions.

A new Row-by-Row Dynamic Source-Line Voltage Control (RRDSV) scheme is proposed to suppress leakage current by two orders of magnitude in the SRAM's for sub-70 nm process technology with sub-1-V VDD. This two-order leakage reduction is caused from the cooperation of reverse body-to-source biasing and Drain Induced Barrier Lowering (DIBL) effects. In addition, metal shields are proposed to be inserted between the cell nodes and the bit lines not to allow the cell nodes to be flipped by the external bit-line coupling noise in this paper. A test chip has been fabricated to verify the effectiveness of the RRDSV scheme with the metal shields by using 0.18-µm CMOS process. The retention voltages of SRAM's with the metal shields are measured to be improved by as much as 40-60 mV without losing the stored data compared to the SRAM's without the shields.

A simple analytical model based on Delayed Quadratic (DQ) Transfer Function approximation is proposed for estimating waveforms of inductive single-line interconnects in VLSI's. An expression for overshoot voltage is derived by the model within 17% error for the line width less than 10 times the minimum line width and typical input signal. A delay expression is also proposed within 15% for the same condition. The strength of the inductive effect is shown to be expressed by a closed-form expression, A=2(L(CT+0.5C))1/2/(RT(CT+CJ)+RTC+RCT+0.4RC). By using the criteria, a scaling trend of inductive effects in VLSI's is discussed. It is shown that the inductive effect of single-line, minimum-width VLSI interconnect peaks off at 90 nm based on the ITRS predicted parameters.